To address the many questions on layout using eGaN FETs, EPC developed five half bridge topology layout designs with up to four FETs per switch connected in parallel. As can be seen on this slide the key differences between each of the designs are as follows: designs A and B are on one side of the PCB and designs C, D, and E have eGaN FETs on both sides of the PCB. Design A is based on minimizing the supply decoupling inductance and design B groups all the gates of the switch very tightly in the center of the FET switch cluster. The upper switch FETs are placed on the top-side of the PCB in design C and the bottom switch FETs are on the bottom-side of the PCB and all of the gates of the switch are grouped very tightly in the center of the FET switch cluster. Designs D and E place all the gates of the switch very tightly in the center of the FET switch cluster and divide the switches evenly over the two sides of the PCB with a side by side half bridge topology layout. Switching current exits lengthwise from the structure in design D and in design E the switching current exits widthwise from the structure.