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The figure here shows the normal power ON/OFF sequence when the WDEN pin is controlled by an external signal. Once the VDD goes higher than UVLO, an internal oscillator for the digital block starts. Then after RSTIN voltage reaches the under voltage detection release threshold, BIST starts to do a self test. If the self test is normal, then XRSTOUT goes high after 10 ms of RSTIN under voltage detection release. If BIST is abnormal, XRSTOUT stays low. In addition, the XRSTOUT changes to low whenever at least two of the monitoring functions are detected.
PTM Published on: 2020-02-18
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