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microelectronics
HIGH PERFORMANCE PLL
With an intrinsic period jitter of 50ps RMS, unlike many transceivers,
the WM8804 and WM8805 contribute a negligible level of jitter to
the system.
REMOVAL AND SUPPRESSION OF EXISTING JITTER
The WM8804 and WM8805 are capable of suppressing
pre-existing jitter at frequencies above 100Hz. Most competitive
S/PDIF transceivers only act above 10kHz, with no effect on the low
and medium frequencies which have the greatest impact on audio
quality. The Wolfson PLL technology enables the WM8804 and
WM8805 to lock onto and recover the data and timing from poor
quality input signals, allowing the transceivers to accept S/PDIF
from any source, even if the input signal is severely degraded.
MASTER CLOCK GENERATION
The PLL can be used to synthesise crystal derived clock signals,
without the requirement for any external fi lter, and can operate as
a high quality master timing source for the audio system, reducing
system cost whilst guaranteeing excellent performance.
WORLD HEADQUARTERS
Wolfson Microelectronics plc
Westfi eld House
26 Westfi eld Road
Edinburgh
EH11 2QB
United Kingdom
t: +44 (0)131 272 7000
f: +44 (0)131 272 7001
e: europe@wolfsonmicro.com
USA SALES OFFICE
Wolfson Microelectronics, Inc.
16 8 75 West Bernardo Drive
Suite 280
San Diego
CA 92127
USA
t: +1 (0)858 676 5090
f: +1 (0)858 676 0484
e: usa@wolfsonmicro.com
JAPAN SALES OFFICE
Wolfson Microelectronics plc
23F Sky Building
2-19-12 Takashima
Nishi-ku
Yokohama, 220-0011
Japan
t: +81 (0)45 440 1230
f: +81 (0)45 440 1231
e: japan@wolfsonmicro.com
ASIA PACIFIC SALES OFFICE
Wolfson Microelectronics plc
2F, No.39, Alley 20
Lane 407, Sec. 2
Tiding Boulevard, NeiHu District
Taipei 114
Taiwan
t: +886 (0) 2 875 11600
f: +886 (0)2 875 10201
e: asia@wolfsonmicro.com
CONTACT DETAILS
For more information please visit www.wolfsonmicro.com or sign up for Wolfson eNews at http://www.wolfsonmicro.com/enews
PO-FL-8804/05-05/07
WM8804 and WM8805 S/PDIF Transceivers
S/PDIF (IEC60958-3) compliant
Advanced jitter attenuating PLL with low intrinsic period
jitter of 50ps RMS
PLL clock recovery or crystal derived clock generation
Supports 10MHz – 27MHz crystal clock frequencies
I2S, Left Justifi ed, Right Justifi ed or DSP audio formats
16/20/24 bit Word Lengths
Up to 8 channels of S/PDIF input with 1 channel output
Auto frequency detection and synchronisation
Selectable output status data
Non-audio detection including DOLBYTM and DTSTM
PRODUCT FEATURES PRODUCT DETAILS
© COPYRIGHT 2007, WOLFSON MICROELECTRONICS PLC.
and the wave logo are a registered trademark of Wolfson Microelectronics plc. All other trademarked names, whether indicated as such or not, are the property of their respective owners. The information in
this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Wolfson Microelectronics plc assumes no responsibility for errors and omissions, and disclaims
responsibility for any consequences resulting from the use of information contained in the document.
WM8804
WM8805
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DIAGRAM 1 – COMPETITOR’S PART
Eye Diagram showing narrowing of output eye width as a result of jitter on input
(input jitter passed to output).
DIAGRAM 2 – WOLFSON’S WM8804 AND WM8805
Eye diagram showing maintained eye width as input data as jittered
(input jitter not passed to output).
WFN8804_aw.indd 2WFN8804_aw.indd 2 22/5/07 16:18:5622/5/07 16:18:56