ISO3086T Datasheet by Texas Instruments

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ISO3086T
SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
ISO3086T Isolated 5-V RS-485 Transceiver With Integrated Transformer Driver
1 Features 3 Description
The ISO3086T is an isolated differential line
1• Meets or Exceeds TIA/EIA-485-A transceiver with integrated oscillator outputs that
• Signaling Rate up to 20 Mbps provide the primary voltage for an isolation
• 1/8 Unit Load – Up to 256 Nodes on a Bus transformer. The device is a full-duplex differential
line transceiver for RS-485 and RS-422 applications
• Thermal Shutdown Protection that can easily be configured for half-duplex operation
• Typical Efficiency > 60% (ILOAD = 100 mA) - see by connecting pin 11 to pin 14, and pin 12 to pin 13.
SLUU469 These devices are ideal for long transmission lines
• Low Bus Capacitance 7 pF (Typ) since the ground loop is broken to allow for a much
• 50-kV/µs Typical Transient Immunity larger common-mode voltage range. The symmetrical
• Fail-safe Receiver for Bus Open, Short, Idle isolation barrier of the device is tested to provide
4242 VPK of isolation for 1 minute per VDE between
• Logic Inputs are 5-V Tolerant the bus-line transceiver and the logic-level interface.
• Bus-Pin ESD Protection Any cabled I/O can be subjected to electrical noise
– 11-kV HBM Between Bus-Pins and GND2 transients from various sources. These noise
– 6-kV HBM Between Bus-Pins and GND1 transients can cause damage to the transceiver
• Safety and Regulatory Approvals and/or near-by sensitive circuitry if they are of
sufficient magnitude and duration. These isolated
– 4242 VPK Basic Insulation per DIN V VDE V devices can significantly increase protection and
0884-10 and DIN EN 61010-1 reduce the risk of damage to expensive control
– 2500 VRMS Isolation for 1 minute per UL 1577 circuits.
– CSA Component Acceptance Notice 5A, IEC The ISO3086T is specified for use from –40°C to
60950-1 and IEC 61010-1 Standards 85°C.
2 Applications Device Information(1)
• Isolated RS-485/RS-422 Interfaces PART NUMBER PACKAGE BODY SIZE (NOM)
• Factory Automation ISO3086T SOIC (16) 10.30 mm × 7.50 mm
• Motor/Motion Control (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• HVAC and Building Automation Networks
• Networked Security Stations
Typical Application Circuit
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features.................................................................. 18 Detailed Description............................................ 14
8.1 Overview ................................................................. 14
2 Applications ........................................................... 18.2 Functional Block Diagram....................................... 14
3 Description ............................................................. 18.3 Feature Description................................................. 15
4 Revision History..................................................... 28.4 Device Functional Modes........................................ 17
5 Pin Configuration and Functions......................... 39 Application and Implementation ........................ 20
6 Specifications......................................................... 39.1 Application Information............................................ 20
6.1 Absolute Maximum Ratings ...................................... 39.2 Typical Application ................................................. 20
6.2 ESD Ratings.............................................................. 410 Power Supply Recommendations ..................... 23
6.3 Recommended Operating Conditions....................... 411 Layout................................................................... 23
6.4 Thermal Information.................................................. 411.1 Layout Guidelines ................................................. 23
6.5 Power Rating............................................................. 411.2 Layout Example .................................................... 24
6.6 Electrical Characteristics: Driver............................... 512 Device and Documentation Support ................. 25
6.7 Electrical Characteristics: Receiver .......................... 512.1 Documentation Support ........................................ 25
6.8 Transformer Driver Characteristics........................... 512.2 Community Resources.......................................... 25
6.9 Supply Current and Common-Mode Transient
Immunity..................................................................... 612.3 Trademarks........................................................... 25
6.10 Switching Characteristics: Driver ............................ 612.4 Electrostatic Discharge Caution............................ 25
6.11 Switching Characteristics: Receiver........................ 612.5 Glossary................................................................ 25
6.12 Typical Characteristics............................................ 713 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information ................ 10 Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2011) to Revision D Page
• Added Feature Item "Meets or Exceeds TIA/EIA-485"........................................................................................................... 1
• VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (July 2011) to Revision C Page
• Added Note 1 to the TRANSFORMER DRIVER CHARACTERISTICS table........................................................................ 5
• Changed the TRANSFORMER DRIVER CHARACTERISTICS table - fSt Test Conditions From: .VCC1 = 9V To: VCC1
= 2.4 and Changed the TYP value From: 230 To: 350 kHz................................................................................................... 6
Changes from Revision A (March 2011) to Revision B Page
• Deleted the MIN and MAX values from rows, tr_d, tf_D, and tBBM of the TRANSFORMER DRIVER
CHARACTERISTICS table..................................................................................................................................................... 6
Changes from Original (January 2011) to Revision A Page
• Changed the Features and Description.................................................................................................................................. 1
• Changed the data sheet From: Preview To: Production ........................................................................................................ 1
• Added Figure 34 Typical Application Circuit........................................................................................................................... 3
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GND2
GND2
NC
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D
D1
DE
VCC1
GND1
D2
VCC2
ISO3086T
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SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A 14 I Non-inverting Receiver Input
B 13 I Inverting Receiver Input
D1 1 O Transformer Driver Terminal 1, Open Drain Output
D2 2 O Transformer Driver Terminal 2, Open Drain Output
D 8 I Driver Input
DE 7 I Driver Enable Input
GND1 3 – Logic-side Ground
GND2 9, 15 – Bus-side Ground. Both pins are internally connected.
NC 10 – No Connect. This pin is not connected to any internal circuitry.
R 5 O Receiver Output
RE 6 I Receiver Enable Input. This pin has complementary logic.
VCC1 4 – Logic-side Power Supply
VCC2 16 – Bus-side Power Supply
Y 11 O Non-inverting Driver Output
Z 12 O Inverting Driver Output
6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VCC1, VCC2 Input supply voltage(2) –0.3 6 V
VA,VB,VY,VZVoltage at any bus I/O terminal (A, B, Y, Z) –9 14 V
VD1,VD2 Voltage at D1, D2 14 V
V(TRANS) Voltage input, transient pulse through 100Ω, see Figure 27 (A, B,Y, Z) –50 50 V
VIVoltage input at D, DE or RE terminal –0.5 7 V
IOReceiver output current –10 10 mA
ID1, ID2 Transformer Driver Output Current 450 mA
TJMaximum junction temperature 170 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
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6.2 ESD Ratings
VALUE UNIT
Bus pins and GND1 ±6000
Human body model (HBM), per ANSI/ESDA/JEDEC JS- Bus pins and GND2 ±11000
001(1)
Electrostatic
V(ESD) All pins ±4000 V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model (MM), ANSI/ESDS5.2-1996 ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
3.3 V Operation 3 3.3 3.6
VCC1 Logic-side supply voltage V
5 V Operation 4.5 5 5.5
VCC2 Bus-side supply voltage 4.5 5 5.5 V
VIor VIC Voltage at any bus terminal (separately or common-mode) –7 12 V
RE 2 VCC1
VIH High-level input voltage V
D, DE 0.7 VCC1
RE 0 0.8
VIL Low-level input voltage V
D, DE 0.3 VCC1
A with respect to B –12 12
VID Differential input voltage V
Dynamic See Figure 16
RLDifferential load resistance 54 60 Ω
Driver –60 60
IOOutput Current mA
Receiver –8 8
TAAmbient temperature –40 85 °C
TJOperating junction temperature –40 150 °C
1 / tUI Signaling Rate 20 Mbps
6.4 Thermal Information
ISO3086T
THERMAL METRIC(1) DW (SOIC) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 80.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43.8 °C/W
RθJB Junction-to-board thermal resistance 49.7 °C/W
ψJT Junction-to-top characterization parameter 13.8 °C/W
ψJB Junction-to-board characterization parameter 41.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Rating
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
VCC1 = VCC2 = 5.5V, TJ= 150°C, RL= 54Ω,
CL= 50pF (Driver), CL= 15pF (Receiver),
PDMaximum device power dissipation 490 mW
Input a 10 MHz 50% duty cycle square wave
to Driver and Receiver
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6.6 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO= 0 mA, no load 3 4.3 VCC2
RL= 54 Ω(RS-485), See Figure 17 1.5 2.3
|VOD| Differential output voltage magnitude V
RL= 100 Ω(RS-422), See Figure 17 2 2.3
Vtest from –7 V to +12 V, SeeFigure 18 1.5
Change in magnitude of the differential
Δ|VOD| See Figure 17 and Figure 18 –0.2 0 0.2 V
output voltage
VOC(SS) Steady-state common-mode output voltage 1 2.6 3 V
Figure 19
Change in steady-state common-mode
ΔVOC(SS) –0.1 0.1 V
output voltage
VOC(pp) Peak-to-peak common-mode output voltage See Figure 19 0.5 V
IIInput current D, DE, VIat 0 V or VCC1 –10 10 µA
VYor VZ= 12 V, 1
VCC2 = 0 V or 5 V, DE = 0 V
High-impedance state output current, Y or Z Other bus pin
IOZ µA
pin at 0 V
VYor VZ= –7 V, –1
VCC2 = 0 V or 5 V, DE = 0 V
Other bus pin
IOS(1) Short-circuit output current –7 V ≤VYor VZ≤12 V –250 250 mA
at 0 V
(1) This device has thermal shutdown and output current limiting features to protect in short-circuit fault condition.
6.7 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going input threshold voltage IO= –8 mA –85 –10 mV
VIT(–) Negative-going input threshold voltage IO= 8 mA –200 –115 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 30 mV
VCC1 = 3.3 V VCC1–0.4 3.1
VID = 200 mV, IO= –8 mA,
VOH High-level output voltage V
See Figure 23 VCC1 = 5 V 4 4.8
VCC1 = 3.3 V 0.15 0.4
VID = 200 mV, IO= 8 mA,
VOL Low-level output voltage V
See Figure 23 VCC1 = 5 V 0.15 0.4
IO(Z) High-impedance state output current VO= 0 or VCC1, RE = VCC1 –1 1 µA
VAor VB= 12 V 40 100
VAor VB= 12 V, VCC2 = 0 60 130
Other input
IA, IBBus input current µA
at 0 V
VAor VB= –7 V –100 –40
VAor VB= –7 V, VCC2 = 0 –100 –30
IIH High-level input current, RE VIH = 2. V –10 10 µA
IIL Low-level input current, RE VIL = 0.8 V –10 10
RID Differential input resistance A, B 96 kΩ
CID Differential input capacitance VI= 0.4 sin (4E6πt) + 0.5 V 7 pF
6.8 Transformer Driver Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 5 V ± 10%, D1 and D2 connected to 350 450 610
transformer
fOSC Oscillator frequency kHz
VCC1 = 3.3 V ± 10%, D1 and D2 connected to 300 400 550
transformer
RON Switch on resistance D1 and D2 connected to 50Ωpull-up resistors 1 2.5 Ω
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Transformer Driver Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 5 V ± 10%, see Figure 29,(1) 80
tr_D D1, D2 output rise time ns
VCC1 = 3.3 V ± 10%, see Figure 29,(1) 70
VCC1 = 5 V ± 10%, see Figure 29,(1) 55
tf_D D1, D2 output fall time ns
VCC1 = 3.3 V ± 10%, see Figure 29,(1) 80
fSt Startup frequency VCC1 = 2.4 V, D1 and D2 connected to transformer 350 kHz
VCC1 = 5 V ± 10%, see Figure 29,(1) 38
tBBM Break before make time delay ns
VCC1 = 3.3 V ± 10%, see Figure 29,(1) 140
(1) D1 and D2 connected to 50Ωpull-up resistors
6.9 Supply Current and Common-Mode Transient Immunity
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 3.3 V ±10% 5 8
Logic-side quiescent DE and RE = 0 V or VCC1 (Driver and Receiver
ICC1(1) mA
supply current Enabled or Disabled), D = 0 V or VCC1, No load VCC1 = 5 V ±10% 7 12
RE = 0 V or VCC1, DE = 0 V (driver disabled), No load 10 15
Bus-side quiescent
ICC2(1) mA
supply current RE = 0 V or VCC1, DE = VCC1 (driver enabled), D = 0 V or VCC1, No Load 10 15
Common-mode
CMTI See Figure 28, VI= VCC1 or 0 V 25 50 kV/µs
transient immunity
(1) ICC1 and ICC2 are measured when device is connected to external power supplies, VCC1 and VCC2. In this case, D1 and D2 are open and
disconnected from external transformer.
6.10 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 25 45
PWD(1) Pulse width distortion (|tPHL – tPLH|) See Figure 20 1 7.5 ns
tr, tfDifferential output signal rise time and fall time 7 15
tPZH, Propagation delay, high-impedance-to-high-level output, See Figure 21 25 55 ns
tPHZ Propagation delay, high-level-to-high-impedance output DE at 0 V
tPLZ, Propagation delay, low-level to high-impedance output, See Figure 22,25 55 ns
tPZL Propagation delay, high-impedance to low-level output DE at 0 V
(1) Also known as pulse skew
6.11 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 103 125
tsk(p) Pulse skew (|tPHL – tPLH|) See Figure 24 3 15 ns
tr, trOutput signal rise and fall time 1
tPHZ, Propagation delay, high-level to high-impedance output See Figure 25, DE at 0 V 11 22
tPZH Propagation delay, high-impedance to high-level output ns
tPLZ, Propagation delay, low-level to high-impedance output See Figure 26, DE at 0 V 11 22
tPZL Propagation delay, high-impedance to low-level output
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100
102
104
106
108
110
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
Reveiver Propagation Delay - ns
tPHL
tPLH
V = 3.3 V,
V = 5 V,
C = 15 pF
CC1
CC2
L
97
98
99
100
101
102
103
104
105
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
tPHL
tPLH
V = V = 5 V,
C = 15 pF
CC1 CC2
L
Reveiver Propagation Delay - ns
20
22
24
26
28
30
32
34
Driver Propagation Delay - ns
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
tPHL
tPLH
V = 3.3 V,
V = 5 V,
R = 54 ,
C = 50 pF
CC1
CC2
L
L
W
0 5 10 15 20
Signaling Rate - Mbps
0
5
10
15
20
25
I - Supply Current - mA
CC
I @ 5 V
CC2
I @ 5 V
CC1
I @ 3.3 V
CC1
No Load
TA = 25°C,
PRBS Data 2 - 1
16
0 5 10 15 20
Signaling Rate - Mbps
I @ 3.3 V
CC1
I @ 5 V
CC1
I @ 5 V
CC2
Driver: R = 54 , C = 50 pF,
Receiver: C = 15 pF,
TA = 25°C,
PRBS Data 2 - 1
L L
L
W
16
0
10
20
30
40
50
60
I - Supply Current - mA
CC
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6.12 Typical Characteristics
Figure 1. Supply Current vs Signaling Rate (No Load) Figure 2. Supply Current vs Signaling Rate (With Load)
Figure 4. Driver Propagation Delay vs Free-Air Temperature
Figure 3. Driver Propagation Delay vs Free-Air Temperature
Figure 5. Receiver Propagation Delay vs Free-Air Figure 6. Receiver Propagation vs Free-Air Temperature
Temperature
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0 10 20 30 40 50 60 70
I - Load Current - mA
L
V = 5 V
CC2
V = 5.5 V
CC2
V = 4.5 V
CC2
T = 25°C
A
0
0.5
1
1.5
2
2.5
3
3.5
V - Differential Output Voltage - V
OD
100 W
50 W
0 1 2 3 4 5
V - Output Voltage - V
O
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
I - Output Current - mA
O
T = 25°C,
V = 5 V
A
CC1
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
tf
tr
V = V = 5 V,
C = 15 pF
CC1 CC2
L
400
500
600
700
800
900
1000
1100
1200
1300
1400
Receiver Rise, Fall Time - ps
600
700
800
900
1000
1100
1200
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
Receiver Rise, Fall Time - ps
V = 3.3 V,
V = 5 V,
C = 15 pF
CC1
CC2
L
tf
tr
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
V = V = 5 V,
R = 54 ,
C = 50 pF
CC1 CC2
L
L
W
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Driver Rise, Fall Time - ns
tr
tf
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Driver Rise, Fall Time - ns
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
tf
tr
V = 3.3 V,
V = 5 V,
R = 54 ,
C = 50 pF
CC1
CC2
L
L
W
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Typical Characteristics (continued)
Figure 8. Driver Rise, Fall Time vs Free-Air Temperature
Figure 7. Driver Rise, Fall Time vs Free-Air Temperature
Figure 10. Receiver Rise, Fall Time vs Free-Air Temperature
Figure 9. Receiver Rise, Fall Time vs Free-Air Temperature
Figure 12. Receiver High-Level Output Current vs High-
Figure 11. Driver Differential Output Voltage vs Load Level Output Voltage
Current
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1.98
2
2.02
2.04
2.06
2.08
2.1
-40 -15 10 35 60 85
T - Free-Air Temperature - °C
A
V - Differential Output Voltage - V
OD
V = 5 V,
R = 54
CC2
LW
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 2 4 6 8 10 12 14 16 18 20
Signaling Rate - Mbps
V - Differential Input Voltage - pk
ID
-60
-40
-20
0
20
40
60
-7 -4 -1 2 5 8 11
V - Bus Input Voltage - V
I
I - Bus Input Current - A
Im
T = 25°C,
V = 5 V
A
CC2
0
10
20
30
40
50
60
70
80
90
0 1 2 3 4 5
V - Output Voltage - V
O
I - Output Current - mA
O
T = 25°C,
V = 5 V
A
CC1
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Typical Characteristics (continued)
Figure 13. Receiver Low-Level Output Current vs Low-Level Figure 14. Input Bias Current vs Bus Input Voltage
Output Voltage
Figure 16. Recommended Minimum Differential Input
Figure 15. Differential Output Voltage vs Free-Air Voltage vs Signaling Rate
Temperature
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CL= 50 pF
Input
Generator 50
S 1
RL= 110
CL includes fixture and
instrumentation
capacitance
D
Y
Z
DE
±20 %
VO
VI
1 %
±
W
W
GND1 GND2
50% 50%
3 V
VOH
0 V
tpZH
50%
90%
0 V
VO
VI
»
Generator: PRR = 50 kHz, 50% duty
cycle, t <6ns, t <6ns, Z = 50
r f O W
tpHZ
D S1
3 V Y
0 V Z
RL=54 L= 50pF
50
D
Y
Z
DE
VI
Input
Generator
±20%
±1%
W
W
Generator: PRR = 100 kHz, 50 % duty cycle,
tr< 6ns, t f<6 ns , ZO= 50W
includes fixture and
instrumentation capacitance
C
L
C
VCC1
GND1
VOD 50%
3 V
tf
tr
tpLH
10%
90%
VI
90%
10%
50%
50 %50 %
VOD
VOD(H)
VOD(L)
tpHL
VOC
ZVZ
VY
Y
VOC(SS)
OC(p-p)
V
Generator: PRR= 100 kHz, 50 % duty
cycle, t r< 6ns , t f<6 ns , ZO= 50W
Input
Input
II
VI
D
DE
Y
ZVOD
27
±1%
W
VCC1
GND1 GND2
GND2
GND1
IY
IZ
VZVYVOC
27
±1%
W
0 or
II
VI
D
DE
Y
Z
VZVY
VOD
IY
IZ
GND2GND1
VCC1
VCC1
GND2GND1
RL
375
375
60
.+
-
D
DE
Y
Z
W
W
W
VCC2
0 or 3 V
GND2
VOD V =
-7 V to 12 V
TEST
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7 Parameter Measurement Information
Figure 17. Driver VOD Test and Current Definitions Figure 18. Driver VOD With Common-Mode Loading
Test Circuit
Figure 19. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
Figure 20. Driver Switching Test Circuit and Voltage Waveforms
Figure 21. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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Product Folder Links: ISO3086T
VCC
Input
Generator 50
R
A
B
CL includesfixture
andinstrumentation
capacitance
RE
VI
VO
W
CL= 15 pF ±20 %
S1
W
1 k ±1 %
1.5 V
0 V
Generator: PRR =100 kHz , 50 % duty cycle ,
r
<6ns , t f<6ns, ZO= 50 W
t
50%
V
OH
tpZH
50%
3 V
0 V
90%
VI
V
O
0 V
50%
»
tpHZ
Input
Generator
1.5 V
CL includesfixtureand
instrumentationcapacitance
A
B
R
±20 %
VO
VI
RE
50 W
CL= 15 pF
Generator: PRR =100 kHz , 50 % duty cycle,
r< 6ns , t f< 6ns , ZO= 50 W
t
50 % 50 %
3 V
VOH
VOL
tf
tr
tpLH
10 %
90 %
50 % 50 %
0 V
VO
VI
tpHL
VID
IO
A
B
R
IB
IA
V
IC
V
A
VB
VB
VA+
2
VO
CL= 50 pF
Input
Generator 50
S1 RL= 110
VCC2
D
Y
Z
DE
VI
±20 %
±1%
VO
W
W
GND1 GND2
CL includes fixture and
instrumentation
capacitance
Generator: PRR=50 kHz, 50% duty cycle,
r< 6ns, t f< 6ns, Z
O= 50W
t
50%
3 V
VOL
tpZL
10%
0 V
VO
VI
50%
50%
tpLZ
D S1
3 V Y
0 V Z
VCC2
ISO3086T
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SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
Parameter Measurement Information (continued)
Figure 22. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
Figure 23. Receiver Voltage and Current Definitions
Figure 24. Receiver Switching Test Circuit and Waveforms
Figure 25. Receiver Enable Test Circuit and Waveforms, Data Output High
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: ISO3086T
VOL
VOH or
D
R
DE
VCC1
1 kW
RE
54 W
VCC2
GND1
VTEST
GND2
CL= 15 pF
( includesprobeand
jigcapacitance)
C = 0.1 F 1%
m±
A
B
GND 1
C = 0.1 F
m
±1%
S 1
2.0 V
0.8 V
VOL
VOH or
1.5 Vor 0 V
0 Vor 1.5 V
Z
Y
54 W
B
A
R
100 W
±1%
+
–
Pulse Generator
15 ms duration
1% Duty Cycle
t , t 100 ns
r f £
Z
Y
D
100 W
±1%
+
–
DE
0 V or 3 V
0 V or 3 V
RE
VCC
Input
Generator 50
R
A
B
CL includesfixture
andinstrumentation
capacitance
RE
VI
VO
W
CL= 15 pF ±20 %
S1
W
1 k ±1 %
0 V
1.5 V
Generator : PRR =100 kHz , 50% duty cycle ,
r<6ns , t f<6ns , ZO= 50 W
t
50%
3 V
0 V
VI
VCC
VOL
tpZL
VO
50%
50%
10%
tpLZ
ISO3086T
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www.ti.com
Parameter Measurement Information (continued)
Figure 26. Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 27. Transient Over-Voltage Test Circuit
Figure 28. Common-Mode Transient Immunity Test Circuit
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*9 TEXAS INSTRUMENTS
D1
D2
tBBM
90%
10%
10%
90%
tr_D tf_D
tf_D tr_D
tBBM
ISO3086T
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Parameter Measurement Information (continued)
Figure 29. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs
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% WA MM ‘5‘ TEXAS INSTRUMENTS
DE 7
D8
R5
6
RE
Y
Z
B
A
14
11
12
13
NGALVANIC ISOLATIO
D1
2OSC
1
D2
ISO3086T
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8 Detailed Description
8.1 Overview
ISO3086T is an isolated full-duplex differential transceiver with integrated transformer driver. The integrated
transformer driver supports elegant secondary power supply design. This device is rated to provide galvanic
isolation up to 4242 VPK per VDE and 2500 VRMS per UL. It has active-high driver enable and active-low receiver
enable to control the data flow. It is suitable for data transmission up to 20 Mbps.
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = V(Y) – V(Z) is positive. When D is low, the output states reverse, Z turns high, Y becomes low, and VOD is
negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant.
The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-
impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is
enabled, output Y turns high and Z turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT– , the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver
output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver
inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the
bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Insulation and Safety Related Specifications for 16 DW Package
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance(1)) Shortest terminal to terminal distance through air 8 mm
Shortest terminal to terminal distance across the
L(I02) Minimum external tracking (Creepage(1)) 8 mm
package surface
Comparative Tracking Index (Tracking DIN EN 60112 (VDE 0303-11); IEC 60112
CTI 400 V
resistance)
DTI Distance through the insulation Minimum Internal Gap (Internal Clearance) 0.008 mm
Input to output, VIO = 500 V, all pins on each
RIO Isolation resistance side of the barrier tied together creating a two- >1012 Ω
terminal device, TA= 25 °C
VIO = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5
CIO Barrier capacitance Input to output 2 pF
V
CIInput capacitance to ground VI= 0.4 sin (2πft), f = 1 MHz 2 pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
8.3.1.1 IEC 60664-1 Ratings Table
PARAMETER TEST CONDITIONS SPECIFICATION
Material group II
Rated mains voltage ≤150 VRMS I-IV
Overvoltage category / Installation
classification for basic insulation Rated mains voltage ≤300 VRMS I-III
8.3.1.2 DIN V VDE V 0884-10 Insulation Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum working isolation voltage 566 VPK
Method b1, VPR = VIORM × 1.875, 1062 VPK
100% Production test with t = 1 s,
Partial discharge < 5 pC
Method a, After environmental tests subgroup 1, 906
VPR Input to output test voltage VPR = VIORM × 1.6, t = 10 s,
Partial discharge < 5pC
After Input/Output Safety Test Subgroup 2/3, 680
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
t = 60 s (Qualification) 4242 VPK
VIOTM Maximum transient isolation voltage t = 1 s (100% Production)
Tested per IEC 60065, 1.2/50 µs waveform, 3077 VPK
VIOSM Maximum surge isolation voltage VTEST = 1.3 x VIOSM = 4000 VPK (Qualification Test)
RSIsolation resistance VIO = 500 V at TS= 150 °C > 109Ω
Pollution degree 2
(1) Climatic Classification 40/125/21
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0
50
100
150
200
250
300
350
0 50 100 150 200
Temperature - °C
V = V = 5.5 V
CC1 CC2
Safety Limiting Current - mA
ISO3086T
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www.ti.com
8.3.1.3 Regulatory Information
VDE CSA UL
Certified according to DIN V VDE V 0884- Approved according to CSA Component Approved under UL 1577 Component
10(VDE V 0884-10):2006-12 and DIN EN Acceptance Notice 5A, IEC 60959-1 and IEC Recognition Program
61010-1 (VDE 0411-1) 61010-1
Basic Insulation 3000 VRMS Isolation Rating; Single Protection, 2500 VRMS(1)
Maximum Transient Isolation Voltage, 4242 VPK Reinforced insulation per CSA 61010-1-04 and
Maximum Surge Isolation Voltage, 3077 VPK IEC 61010-1 2nd Ed. 150 VRMS working voltage;
Maximum Working Isolation Voltage, 566 VPK Basic insulation per CSA 61010-1-04 and IEC
61010-1 2nd Ed. 600 VRMS working voltage;
Basic insulation per CSA 60950-1-07 and IEC
60950-1 2nd Ed. 760 VRMS working voltage
Certificate Number: 40016131 Master Contract Number: 220991 File Number: E181974
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply. Without current limiting, sufficient power is
dissipated to overheat the die and damage the isolation barrier—potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISSafety input, output, or supply current θJA = 80.5°C/W, VI= 5.5 V, TJ= 170°C, TA= 25°C 327 mA
DW-16
TSMaximum safety temperature 150 °C
The safety-limiting constraint is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is
that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the
recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
Figure 30. Thermal Derating Curve per VDE
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8.4 Device Functional Modes
Table 1 and Table 2 are the function tables for the ISO3086T driver and receiver.
Table 1. Driver Function Table(1)
INPUT ENABLE OUTPUTS
(D) (DE) Y Z
H H H L
L H L H
X L hi-Z hi-Z
X OPEN hi-Z hi-Z
OPEN H H L
(1) H = High Level, L= Low Level, X = Don’t Care, hi-Z = High Impedance (off)
Table 2. Receiver Function Table(1)
DIFFERENTIAL INPUT ENABLE OUTPUT
VID = (VA– VB) (RE) (R)
–0.01 V ≤VID L H
–0.2 V < VID –0.01 V L ?
VID ≤–0.2 V L L
X H hi-Z
X OPEN hi-Z
Open circuit L H
Short Circuit L H
Idle (terminated) bus L H
(1) H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off), ? = Indeterminate
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ISO3086T
16V
Input
B Input
16V
VCC 2
36 kW
36 kW
180 k
16V
Input
A Input
36 k
16V
W
W
36 kW
VCC 2
180 kW
16V
Output
Y and Z Outputs
16V
VCC 2
4
6 .5
W
W
VCC 1
R Output
output
ISO3086T
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www.ti.com
8.4.1 Device I/O Schematics
Figure 31. Equivalent Circuit Schematics
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W
VCC 1
1 M
VCC 1
VCC 1
500 W
W1 M
VCC 1
500 W
DE Input
VCC 1
inputinput
D, InputRE
ISO3086T
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SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
Figure 32. Equivalent Circuit Schematics
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Product Folder Links: ISO3086T
l TEXAS INSTRUMENTS Iscznm
C2
1
2
3
4
5
6
7
8
D1
D2
VCC1
GND1
R
RE
DE
D
VCC2
A
B
GND2
Z
Y
C3
16
14
13
12
11
15
9, 10
OUT
NC
C6
IN
EN
GND
5
1
LDO
1
3
2
C5C4
D1
D2
8
7
6
5
4
3
2
1
C1
X-FMR
ISO3086T
Isolated Supply to
other Components
RS-485 Bus
Interface
Control
Circuitry
R
DR
DE
RE
D
Y
ZR
D
R
RE
DE
D
A
B
B
A
Z
Y
RD
RRE DE D
Z YBA
Master Slave
Slave
R(T)
R(T)
R(T)
R(T)
ISO3086T
SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO308T consists of an RS-485 transceiver commonly used for asynchronous data transmissions. Full-
duplex implementation requires two signal pairs (four wires), and allows each node to transmit data on one pair
while simultaneously receiving data on the other pair. To eliminate line reflections, each cable end is terminated
with a termination resistor, R(T), whose value matches the characteristic impedance, Z0, of the cable. This
method, known as parallel termination, allows for higher data rates over longer cable length.
Figure 33. Half-Duplex Transceiver Configurations
9.2 Typical Application
Figure 34. Typical Application Circuit
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1
16
GND2 ISO
ISO
N
ISO IN IN
1
v C 1 1
= = = = 0.94
1 1 C
v+ 1 +
1 +
C C C
´
9
GN D 2 ISO
9 4
N ISO IN
v R 10
= =
v R + R 10 + 6 10
ISO
GND2 N
ISO IN
Z
v = v
Z + Z
ISO3086T
www.ti.com
SLLSE27D –JANUARY 2011–REVISED OCTOBER 2015
Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
Table 3. Design Parameters
PARAMETER VALUE
Pullup and Pulldown Resistors 1 kΩto 10 kΩ
Decoupling Capacitors 100 nF
9.2.2 Detailed Design Procedure
9.2.2.1 Transient Voltages
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of the ISO3086T are sufficient for all but the most
severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment and can easily exceed insulation ratings. ESD generators simulate static
discharges that may occur during device or equipment handling with low-energy but very high voltage transients.
Figure 35 models the ISO3086T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of the ISO3086T plus those of any other insulation (transformer, etc.), and
we assume stray inductance negligible. From this model, the voltage at the isolated bus return is shown in
Equation 1 and will always be less than 16 V from VN.
(1)
If the ISO3086T are tested as a stand-alone device, RIN= 6 × 104Ω, CIN= 16 × 10-12 F, RISO= 109Ωand
CISO= 10-12 F.
In Figure 35 the resistor ratio determines the voltage ratio at low frequency and it is the inverse capacitance ratio
at high frequency. In the stand-alone case and for low frequency, use Equation 2, or essentially all of noise
appears across the barrier.
(2)
At very high frequency, Equation 3 is true, and 94% of VNappears across the barrier.
(3)
As long as RISO is greater than RIN and CISO is less than CIN, most of transient noise appears across the isolation
barrier, as it should.
TI recommends not testing equipment transient susceptibility with ESD generators or consider product claims of
ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through recessing
or covering connector pins in a conductive connector shell and installer training.
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10
100
0 250 500 750 1000
WORKING VOLTAGE (V IORM) -- V
WORKING LIFE -- YEARS
VIORM at 566 V
28
880120
PK
PK
VN
RIN
CIN
RISO
CISO
SystemGround(GND1)
BusReturn (GND2)
16 V
A, B, Y, orZ
ISO3086T
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www.ti.com
Figure 35. Noise Model
9.2.3 Application Curve
At maximum working voltage, ISO3086T isolation barrier has more than 28 years of life.
Figure 36. Time-Dependent Dielectric Breakdown Test Results
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, TI recommends a 0.1-µF bypass capacitor at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. This device is used in applications where only a single primary-side power supply is available. Isolated
power can be generated for the secondary-side with the help of integrated transformer driver.
11 Layout
11.1 Layout Guidelines
ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 37).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane, and low-frequency signal layer.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least
inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs
on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩto 10-kΩpullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
NOTE
For detailed layout recommendations, see Application Note Digital Isolator Design Guide,
SLLA284.
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Product Folder Links: ISO3086T
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10 mils
10 mils
40 mils FR-4
0r ~ 4.5
Keep this
space free
from planes,
traces, pads,
and vias
Ground plane
Power plane
Low-speed traces
High-speed traces
ISO3086T
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www.ti.com
11.2 Layout Example
Figure 37. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•Isolated, Full-Duplex, 20-Mbps, 3.3-V to 5-V RS-485 Interface (SLUU469)
•Digital Isolator Design Guide (SLLA284)
•Isolation Glossary (SLLA353)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: ISO3086T
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ISO3086TDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO3086T
ISO3086TDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO3086T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
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I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO3086TDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO3086TDWR SOIC DW 16 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO3086TDW DW SOIC 16 40 506.98 12.7 4826 6.6
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
SOIC - 2.65 mm max heightDW 16
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
4224780/A
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4221009/B 07/2016
SOIC - 2.65 mm max heightDW0016B
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
v¢\‘\‘\
www.ti.com
EXAMPLE BOARD LAYOUT
(9.75)
R0.05 TYP
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
16X (2)
16X (0.6)
4221009/B 07/2016
SOIC - 2.65 mm max heightDW0016B
SOIC
SYMM
SYMM
SEE
DETAILS
1
89
16
SYMM
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:4X
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SEE
DETAILS
vm““‘+\‘\‘ maimémmfi A fig % $ E A
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
(9.75)
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4221009/B 07/2016
SOIC - 2.65 mm max heightDW0016B
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
89
16
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
SYMM
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
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