SN65LVPE504 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS HH
EQ
TX
1-4+
TX
1-4-
RX
1-4+
RX
1-4-
Detect
VBB_TX
Receiver/
Equalizer Driver
RST#
CHANNEL
1-4
DE
Receiver/
Equalizer
EN_RXD
E
Q
U
A
L
I
Z
E
R
LossofSignal
Detector
LowPower
Controller
PS2
OS
RX
PS1
OS
SQ_TH
DualTermination
TX
SN65LVPE504
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Quad Channel (Half X4 Lane) PCIe Redriver/Equalizer
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1FEATURES DESCRIPTION
4 Identical Channel PCIe Equalizer/Redriver
Support for Both PCIe Gen I (2.5Gbps) and The SN65LVPE504 is a quad channel, half four lane
PCIe redriver and signal conditioner supporting data
Gen II (5.0 Gbps) Speed rates of up to 5.0Gbps. The device complies with
Selectable Equalization, De-emphasis, and PCIe spec revision 2.1, supporting electrical idle and
Output Swing power management modes.
Per Channel Receive Detect (Lane Detection) Programmable EQ, De-Emphasis and Amplitude
Selectable Receiver Electrical Idle Threshold Swing
Control The SN65LVPE504 is designed to minimize the
Low Operating Power Modes signal degradation effects such as crosstalk and
Supports Three Low-Power Modes to inter-symbol interference (ISI) that limits interconnect
Enable up to 80% Lower Operating Power distance between two devices. The input stage of
each channel offers selectable equalization settings
Excellent Jitter and Loss Compensation that can be programmed to match loss in the
Capability to 50" of 4-mil SL on FR4 channel. The differential outputs provide selectable
Small Foot Print – 42 Pin 9 × 3.5 TQFN de-emphasis to compensate for the anticipated
Package distortion PCIe signal will experience. Both
High Protection Against ESD Transient equalization and de-emphasis levels for all 4
channels are controlled by the setting of signal
HBM: 6,000 V control pins EQ, DE and OS.
CDM: 1,000 V See Table 1 for EQ, DE and OS setting details.
MM: 200 V spacer
APPLICATIONS
PC MB, Docking Station, Server,
Communication Platform, Backplane and
Cabled Application
Figure 1. Data Flow Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DEVICE OPERATION
Device PowerOn
Device initiates internal power-on reset after Vcc has stabilized. External reset can also be applied at anytime by
toggling RST pin. External reset is recommended after every device power-up. After 50µs (MAX) from the
application of RST, device samples the state of EN_RXD, if it is set H device will enter Rx.Detect state where
each of the four channels will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L,
automatic RX detect function is disabled and all channels are enabled with their termination set to ZRX_DC.
Receiver Detection
While EN_RXD pin is H and device is not in reset state (RST is H), LVPE504 performs RX.Detect on all its 4
channels indefinitely until remote termination is detected on at least one channel. When termination is detected
on 1 CH, RX.Detect cycle is limited to 5 more tries on the other channels. At the end of 5th try those channels
which failed to detect remote termination will be turned off to save power and their Rx termination is set to
ZRX-HIGH. In the event device detects only three channels, all four channels are enabled.
Automatic Rx detection feature on all four channels can be forced off by driving EN_RXD low. In this state all
four channels input termination are set to ZRX_DC.
Standby Mode
This is low power state triggered by RST = L. In standby mode receiver termination resistor for each of the four
channels is switched to ZRX-HIGH of >50 kΩand transmitters are pulled to Hi-Z state. Device power is reduced to
<10mW (TYP). To get device out of standby mode RST is toggled L-H.
Electrical Idle Support
A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode
voltage. LVPE504 detects an electrical idle state when RX± input voltage of the associated channel falls below
VEID_TH min and stays in this state for at least 20ns. After detection of an electrical idle state in a given channel
the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VEID_TH max, normal
operation is restored and output start passing input signal. Electrical idle exit and entry time is specified at < 8 ns
(MAX).
Electrical idle support is independent for each channel, however to lower active power it is possible to slave
electrical idle function from channel 1 to CH2-CH4. This mode is selected by driving PS2 to H.
Power Save Features
Device supports three power save modes as below:
1. Standby Mode
This mode can be enabled from any state (Rx detect or active) by driving RST L. In this state all 4 channels
have their termination set to ZRX-HIGH and outputs are at Hi-Z. Device power is 10mW (MAX).
2. Auto Low Power Mode
This mode is enabled when PS1 pin is tied H and device has been in active mode, i.e., past Rx detect state
for >250ms (TYP). In this mode anytime Vindiff_p-p falls below selected VEID_TH for a given channel and stays
below VEID_TH for >1µs, the associated CH enters auto low power (ALP) mode where power/CH is reduced
by >80% of normal operating power/CH. A CH will exit ALP mode whenever Vindiff_p-p exceeds max VEID_TH
for that channel. Exit latency from ALP state is 30ns max. To use this mode link latency will need to account
for the ALP exit time for N_FTS. ALP mode is handled by each channel independently based on its input
differential signal level, unless slave mode is activated (PS2=H) when CH1 controls SQ detect of other
channels based on its signal level.
3. Slave Power Mode
This mode is activated by driving PS2 high. Under normal operation squelch detection is handled by each
channel independently. In slave mode SQ detection for CH2, CH3 and CH4 are turned off and squelch
function is slaved to that of CH1. By turning off squelch detection circuitry for three of the four channels
device saves power. To use this feature user must ensure all channels operate simultaneously
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l TEXAS INSTRUMENTS IIIIII [:1
InstrumentationChassis/
I/Oexpansionbox/
DockingStation
PCIe
compliant
cable
Server/PC/Notebook
Mainboard Midplane I/OModule
I/OModule
I/OModule
I/OHub
uP
RSN75LVPE504
R
R
R
R
R
R
Tx
Tx
Tx
Rx
Rx
Rx
x4
x4
x4
Cabled
Backplane
SN65LVPE504
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Squelch Control
Controls electrical idle detect threshold level. Three levels are supported as shown in Table 1.
Beacon Support
With its broadband design, the SN65LVPE504 supports low frequency Beacon signal (as defined by PCIe 2.1
spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All
requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass
beacon signals.
Figure 2. LVPE504 Typical Applications
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VCC
PS2
OS
EN_RXD
RST
VCC
VCC
EQ
SQ_TH
DE
PS1
NC NC
NCNC
GND GND
GND
GND
GND
GND
GND
GND
RX1+ TX1+
TX2+
TX3+
TX4+
RX2+
RX3+
RX4+
RX1– TX1–
TX2–
TX3–
TX4–
RX2–
RX3–
RX4–
VCC
VCC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
RUA Package
(TopView)
SN65LVPE504
SN65LVPE504
SLLSE46 SEPTEMBER 2010
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DEVICE INFORMATION
Figure 3. Flow-Through Pin-Out
PIN FUNCTIONS
PIN I/O TYPE DESCRIPTION
NO. NAME
HIGH SPEED DIFFERENTIAL I/O PINS
3 RX1+
4 RX1–
6 RX2+
7 RX2– Non-inverting and inverting CML differential input for CH 1 and CH 4. These pins are tied to an internal voltage
I, CML bias by dual termination resistor circuit
11 RX3+
12 RX3–
14 RX4+
15 RX4–
36 TX1+
35 TX1– Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage
O, CML bias by termination resistors
33 TX2+
32 TX2–
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PIN FUNCTIONS (continued)
PIN I/O TYPE DESCRIPTION
NO. NAME
HIGH SPEED DIFFERENTIAL I/O PINS (continued)
28 TX3+
27 TX3– Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage
O, CML bias by termination resistors
25 TX4+
24 TX4–
DEVICE CONTROL PIN
40 EN_RXD I, LVCMOS Sets device operation modes per Table 1. Internally pulled to VCC
42 PS2 I, LVCMOS Tying pin to VCC slaves CH2-4 electrical idle and Rx.Detect function to CH1. Internally pulled to GND
18 PS1 I, LVCMOS Select auto-low power save mode per Table 1. Internally pulled to GND
20 SQ_TH(1) I, LVCMOS Squelch threshold level select pin for electrical idle detect per Table 1 Internally pulled to VCC/2
39 RST I, LVCMOS Reset device, input active Low. Internally pulled to VCC
SIGNAL CONDITIONING PINS(1)
21 DE I, LVCMOS Selects de-emphasis settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2
19 EQ I, LVCMOS Selects equalization settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2
41 OS I, LVCMOS Selects output amplitude for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2
POWER PINS
1,9,17,22,30,38 VCC Power Positive supply should be 3.3V ± 10%
5,8,10,13, GND Power Supply ground
26,29,31,34û
(1) Internally biased to Vcc/2 with >200kpull-up/pull-down. When 3-state pins are left as NC, board leakage at the pin pad must be < 1 µA
otherwise drive to Vcc/2 to assert mid-level state.
Table 1. Control Pin Settings
OUTPUT SWING (CH1-CH4) at 5Gbps SQUELCH THRESHOLD (CH1-CH4)
TRANSITION BIT AMPLITUDE MIN DIFFERENTIAL INPUT
OS SQ_TH
(TYP mVpp) (CH1-CH4)
0 800 0 47 mVpp
NC (default) 929 NC (default) 61 mVpp
1 1047 1 83 mVpp
OUTPUT DE-EMPHASIS (CH1-CH4) at 5Gbps INPUT EQUALIZATION (CH1-CH4)
DE OS = NC OS = 0 OS = 1 EQ Equalization dB (at 5Gbps)
NC (default) –3.4dB –2.1dB –4.6dB 0 0
0 –6.2dB –4.9dB –7.2dB NC 7 (default)
1 –10.3dB –9.2dB –11dB 1 15
EN_RXD DEVICE FUNCTION
0 Set input termination to Rx_DC
1 Perform Rx detect after power up
RST DEVICE FUNCTION
0 Device in standby state, inputs set to Hi-Z
1 Device in active mode
PS1 DEVICE FUNCTION
0 Auto-low power mode disabled (default)
1 Auto-low power mode enabled
PS2 DEVICE FUNCTION
0 Electrical Idle and Rx Detect independent for CH1-CH4 (default)
1 CH2-CH4 Electrical Idle and Rx Detect slaved to CH1
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ORDERING INFORMATION(1)
PART NUMBER PART MARKING PACKAGE
SN65LVPE504RUAR LVPE504 42-pin RUA Reel (large)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Supply voltage range(2) VCC –0.5 to 4 V
Differential I/O –0.5 to 4 V
Voltage range Control I/O –0.5 to VCC + 0.5 V
Human body model(3) ±6000 V
Electrostatic discharge Charged-device model(4) ±1000 V
Machine model(5) ±200 V
Continuous power dissipation See Thermal Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A
THERMAL INFORMATION
SN65LVPE504
THERMAL METRIC UNITS
TQFN (42 PINS)
qJA Junction-to-ambient thermal resistance 30
qJCtop Junction-to-case (top) thermal resistance 12
qJB Junction-to-board thermal resistance 10 °C/W
yJT Junction-to-top characterization parameter 0.5
yJB Junction-to-board characterization parameter 9
qJCbot Junction-to-case (bottom) thermal resistance 4.7
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNITS
VCC Supply voltage 3 3.3 3.6 V
CCOUPLING AC Coupling capacitor 75 200 nF
Operating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
under recommended operating conditions
PARAMETER CONDITIONS MIN TYP MAX UNITS
DEVICE PARAMETERS
RST, DEx, EQx, OS = NC, EN_RXD = NC, K28.5
ICC 174 190
pattern at 5 Gbps, VID = 1000mVp-p
PS2 = Vcc; RST, DEx, EQx, OS = NC,
ICCSlave EN_RXD = NC, K28.5 pattern at 5 Gbps, 161 175
VID = 1000mVp-p
Supply current mA
When auto-low power conditions are met,
ICCALP 27 32
PS1 = VCC
ICCALP _Slave PS1, PS2 = VCC and link in EID state 14 18
ICCNO_CONNECT EN_RXD = 1 No termination detected on any CH 2.5
ICCstdby RST = GND 0.1
Maximum data rate 5 Gbps
AutoLPENTRY Auto low power entry time Electrical idle at input, Refer to Figure 7 1 µs
AutoLPEXIT Auto low power exit time After first signal activity, Refer to Figure 7 30 ns
tENB Device enable time RST 0 1 5 50 µs
tDIS Device disable time RST 1 0 0.1 2 µs
EN_RXD = 1, Time to start Rx Detect after power
TRX.Detect Rx.Detect start event 6 µs
up
CONTROL LOGIC
VIH High level Input Voltage 1.4 Vcc V
VIL Low Level Input Voltage –0.3 0.5 V
VHYS Input Hysteresis 150 mV
OS, EQ, DE, SQ_TH, PS1, PS2 = VCC 30
IIH High Level Input Current µA
EN_RXD, RST = VCC 1
PS1, PS2 = GND –1
IIL Low Level Input Current µA
OS, EQ, DE, SQ_TH, EN_RXD, RST = GND –30
RECEIVER AC/DC
Vindiff_p-p RX1-RX4 Input voltage swing AC coupled differential signal (5Gbps) 100 1200 mVp-p
TRX_TJ Max Rx total timing error At device pin (5Gbps) 0.4 UI
Max Rx deterministic timing
TRX_DJ At device pin (5Gbps) 0.3 UI
error
RX1-RX4 Common mode
VCM_RX 0 3.6 V
voltage
RX1-RX4 AC peak common
VinCOM_P 150 mVP
mode voltage
ZRX_DC DC single ended impedance 40 55 60
DC Differential input
ZRX_Diff 80 98 120
impedance
Device in standby mode. Rx termination not
ZRX_High DC Input high impedance powered measured with respect to GND over 200 50 75 k
mV max
Measured at receiver pin: SQ_TH = NC 61
VEID_TH Electrical idle detect threshold SQ_TH = 1 58 83 107 mVpp
SQ_TH = 0 47
50 MHz – 1.25 GHz 10 15
RLRX-DIFF Differential return loss dB
1.25 GHz – 2.5 GHz 8 11
RLRX-CM Common mode return loss 50 MHz – 2.5 GHz 9 14 dB
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ELECTRICAL CHARACTERISTICS (continued)
under recommended operating conditions
PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSMITTER AC/DC
RL = 100±1%, OS = NC, transition Bit 866 929 1031
RL = 100±1%, OS = GND transition Bit 800
RL = 100±1% OS = VCC transition Bit 1047
Differential peak-to-peak
VTXDIFF_P-P mV
RL = 100±1%, DE=NC, OS = 0,1,NC
output voltage 620
on-transition bit
RL = 100±1%, DE=OS = 0,1,NC on-transition bit 456
RL = 100±1%, DE=OS = 0,1,NC on-transition bit 288
–3.0 –3.4 –4.0
OS = NC (Figure 9) for OS = 1 and NC see
De-emphasis level –5.5 –6.2 –6.5 dB
Table 1)–9.0 –10.3 –10.6
TDE De-emphasis width At 5 Gbps 0.9 UI
ZTX_diff DC Differential impedance Defined during signaling 80 100 120
f = 50 MHz – 1.25 GHz 10 20
RLdiff_TX Differential return loss dB
f = 1.25 GHz – 2.5 GHz 8 13
RLCM_TX Common mode return loss f = 50 MHz – 2.5 GHz 6 12 dB
ITX_SC TX short circuit current TX± shorted to GND 44 90 mA
Transmitter DC common-mode Allowed DC CM voltage at TX pins
VTX_CM_DC 1.8 2.2 V
voltage
TX AC common mode voltage Max(Vd+ + Vd–) /2 – Min(Vd+ + Vd–)/2
VTX_CM_AC2 30 100 mVpp
at Gen II speed
TX AC common mode voltage RMS(Vd+ + Vd–)/2 – DCAVG(Vd+ + Vd–)/2
VTX_CM_AC1 3 20 mV
at Gen I speed
VTX_CM_DeltaL0- Absolute Delta DC CM voltage |VTX_CM_DC [L0] – VTX_CM_DC [L0s] | 0 100 mV
L0s during active and idle states
VTX_CM-DC-Line- Absolute delta of DC CM |VTX_CM_DC–D+ [L0] – VTX_CM_DC–D– [L0] |0 25 mV
Delta voltage between D+ and D–
Electrical idle differential peak |VTX-Idle-D+ – VTX-Idle-D–|, LP filtered to remove any
VTX_idle_diff-AC-p 0 1 20 mVpp
output voltage DC component
DC electrical idle differential |VTX_idle-D+ – VTX_idle-D–|, LP filtered to remove any
VTX_idle_diff-DC 1.9 mV
output voltage AC component
Voltage change to allow Positive voltage to sense receiver
Vdetect 600 mV
receiver detect
De-Emphasis = 0 dB,
tR,tFOutput rise/fall time OS = NC (CH 0 and CH 1) 30 55 70 ps
20%-80% of differential voltage at the output
De-Emphasis = 0dB,
tRF_MM Output rise/fall time mismatch OS = NC (CH 0 and CH 1) 20 ps
20%-80% of differential voltage at the output
De-Emphasis = 0dB (CH 0 and CH 1). Propagation
Tdiff_LH, Tdiff_HL Differential propagation delay 280 350 ps
delay between 50% level at input and output
TINTRA_SKEW Output skew (same lane) 5 Gbps 15 ps
TINTER_SKEW Lane to lane skew 5 Gbps –25 25 ps
tidleEntry, tidleExit Idle entry and exit times See Figure 5 8 ns
Ttx_EID_min Minimum time in EID 20 ns
Tx EQUALIZATION AT GEN II SPEED
TXDJ(1) At point A1 in Figure 8, EQ/DE=NC, OS=HIGH 25 60
Residual deterministic jitter At point A2 in Figure 8, EQ/DE=NC, OS=LOW 26 60 ps p-p
At point B in Figure 8, EQ/DE=NC, OS=HIGH 27 60
TXRJ Residual random jitter D24.3 pattern at point A1/A2/B in Figure 8 0.1 psrms
(1) Refer to Figure 8 with ±K28.5 pattern, –3.5dB DE from source AWG
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b TEXAS INSTRUMENTS <— x="" x="" x="" x="" _‘="" x="" \="" ‘4—dfl—b‘="" mode="">
IN
OUT
Tdiff_LH Tdiff_HL
Vcm
IN+
IN-
OUT+
OUT-
Vcm
tidleExit tidleEntry
VEID_TH
80 %
20 %
trtf
AutoLPENTRY
RX_1-4+
PowerSaving
Mode
RX_1-4-
TX_1-4+
TX_1-4-
tidleEntry
VCMRX
VCMTX
AutoLPEXIT
SN65LVPE504
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Figure 4. Propagation Delay
Figure 5. Idle Mode Exit and Entry Delay
Figure 6. Output Rise and Fall Times
Figure 7. Auto Low Power Mode Timing (when enabled)
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Y = 8", 5milSL on
FR4
CH
X = 40", 4milSL on
FR4
AWG*
JitterMeasurement
A1
5 GbpsSignalGen.
K28.5 pattern, 800mVpp
2" 2"
Y = 23", 5milSL on
FR4
CH
X = 25", 4milSL on
FR4
AWG*
JitterMeasurement
A2 B
5 GbpsSignalGen.
K28.5 pattern, 800mVpp
2" 2"
SN65LVPE504
SLLSE46 SEPTEMBER 2010
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Figure 8. Jitter Measurement Setup
Figure 9. Output De-Emphasis Levels
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Input Trace = 4", Output Trace = 8"
EQ = 0 dB, OS = 833 mVpp, DE = 1.9 dB-
Input Trace = 4", Output Trace = 16"
EQ = 0 dB, OS = 1166 mVpp, DE = 4.9 dB-
Input Trace = 4", Output Trace = 28"
EQ = 0 dB, OS = 1166 mVpp, DE = 7.4 dB-
Input Trace = 16", Output Trace = 4"
EQ = 0 dB, OS = 833 mVpp, DE = 1.9 dB-
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TYPICAL CHARACTERISTICS
TYPICAL EYE DIAGRAM AND PERFORMANCE CURVES
Input Signal Characteristics – VID = 1000mVpp, DE = –3.5 dB, Pattern = K28.5
Device Operating Conditions: VCC = 3.3 V, Temp = 25°C
All trace are 4 mils
PCIe Gen I and Gen II compliance mask shown
AT GEN II SPEED
Figure 10. Figure 11.
Figure 12. Figure 13.
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Input Trace = 28", Output Trace = 4"
EQ = 7 dB, OS = 833 mVpp, DE = 1.9 dB-
1
Input Trace = 36", Output Trace = 4"
EQ = 7 dB, OS = 833 mVpp, DE = .9 dB-
Input Trace = 48", Output Trace = 4"
EQ = 15 dB, OS = 833 mVpp, DE = 1.9 dB-
Input Trace = 4", Output Trace = 8"
EQ = 7 dB, OS = 833 mVpp, DE = 1.9 dB-
Input Trace = 4", Output Trace = 16"
EQ = 7 dB, OS = 1166 mVpp, DE = 4.9 dB-
SN65LVPE504
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Figure 15.
Figure 16.
AT GEN I SPEED
Figure 17. Figure 18.
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Input Trace = 4", Output Trace = 28"
EQ = 7 dB, OS = 1166 mVpp, DE = 7.4 dB-
Input Trace = 16", Output Trace = 4"
EQ = 7 dB, OS = 833 mVpp, DE = 1.9 dB-
Input Trace = 28", Output Trace = 4"
EQ = 15 dB, OS = 833 mVpp, DE = 1.9 dB-
1
Input Trace = 36", Output Trace = 4"
EQ = 15 dB, OS = 833 mVpp, DE = .9 dB-
Input Trace = 48", Output Trace = 4"
EQ = 15 dB, OS = 833 mVpp, DE = 1.9 dB-
SN65LVPE504
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TYPICAL CHARACTERISTICS (continued)
Figure 19. Figure 20.
Figure 21. Figure 22.
Figure 23.
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65LVPE504RUAR ACTIVE WQFN RUA 42 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVPE504
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVPE504RUAR WQFN RUA 42 3000 330.0 16.4 3.8 9.3 1.0 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVPE504RUAR WQFN RUA 42 3000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WQFN - 0.8 mm max heightRUA 42
PLASTIC QUAD FLATPACK - NO LEAD
9 x 3.5, 0.5 mm pitch
4226504/A
I 1 i :E 41+ , CCCCCCCCECCCCCCCC\ , [a Q ‘ 7 m \ i a 4 “73333333333333? ,TT , Vt Lrw r|m|L flfl
www.ti.com
PACKAGE OUTLINE
3.6
3.4
9.1
8.9
0.8
0.6
0.05
0.00
2X 8
38X 0.5
2X 1.5
42X 0.5
0.3
42X 0.3
0.2
7.55 0.1
2.05 0.1
(0.1) TYP
WQFN - 0.8 mm max heightRUA0042A
PLASTIC QUAD FLATPACK - NO LEAD
4219139/A 03/2020
0.08 C
0.1 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PIN 1 INDEX AREA
SEATING PLANE
PIN 1 ID
SYMM
EXPOSED
THERMAL PAD
SYMM
1
17
18 21
22
38
39
42
43
SCALE 1.800
A
B
C
/5 7 7 7,7,7 fig? Cpcho v (L EB@** L11 F: l 7 mfg? WEEEE , w‘l g 3F, 87 M Him ““7 o ”7 $$fi$%@$x\7 v7¢
www.ti.com
EXAMPLE BOARD LAYOUT
38X (0.5)
(R0.05) TYP
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
1.17 TYP
(0.775)
TYP
42X (0.6)
42X (0.25)
(3.3)
(8.8)(7.55)
(2.05)
( 0.2) TYP
VIA
(3.525) TYP
WQFN - 0.8 mm max heightRUA0042A
PLASTIC QUAD FLATPACK - NO LEAD
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SEE SOLDER MASK
DETAIL
1
17
18 21
22
38
39
42
43
METAL EDGE
SOLDER MASK
OPENING
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
fl 4 j * fl mmgfimmagmmfi Ev? “““ E 8+; x? H‘mjrfii mafia 7 E V E E E % flat? $¢$$$$$ “““ P
www.ti.com
EXAMPLE STENCIL DESIGN
12X (0.92)
12X (0.97)
(0.585)
TYP
(0.56) TYP
42X (0.6)
42X (0.25)
38X (0.5)
(3.3)
(8.8)
(R0.05) TYP
WQFN - 0.8 mm max heightRUA0042A
PLASTIC QUAD FLATPACK - NO LEAD
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SYMM
SYMM
1
17
18 21
22
38
39
42
43
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