SN74AUP2G00 Datasheet by Texas Instruments

Q; TEXAS INSTRUMENTS a M M, M W W W L, L, ,JL ,4 *1 r1 r’ ,4 ‘ W L, J] if, 2‘ U, [E g 31 BEBE Emmi
DCU PACKAGE
(TOP VIEW)
18
27
3 6
1A
1B
2Y
GND 45
VCC
1Y
2B
2A
RSE PACKAGE
(TOP VIEW)
17
26
8
35
4
VCC
1Y
2B
2A
GND
1A
1B
2Y
YFP PACKAGE
(TOP VIEW)
18VCC
27
1Y
3 6 2B
1A
1B
2Y
GND 452A
18
27
3 6
1A
1B
2Y
GND 45
VCC
1Y
2B
2A
DQE PACKAGE
(TOP VIEW)
D1 D2
C1 C2
B1 B2
A1 A2
(A) Single, dual, and triple gates
Static-Power Consumption
(µA)
AUP
AUP
3.3-V
Logic(A)
0%
20%
40%
60%
80%
100%
Dynamic-Power Consumption
(pF)
AUP
AUP
3.3-V
Logic(A)
0%
20%
40%
60%
80%
100%
Switching Characteristics
at 25 MHz(A)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25 30 35 40 45
Time (ns)
Voltage (V)
OutputInput
(A) SN74AUP2Gxx data at C = 15 pF.
L
SN74AUP2G00
www.ti.com
SCES752C –SEPTEMBER 2009REVISED MAY 2010
LOW-POWER DUAL 2-INPUT POSITIVE-NAND GATE
Check for Samples: SN74AUP2G00
1FEATURES
Available in the Texas Instruments NanoStar™ Optimized for 3.3-V Operation
Package 3.6-V I/O Tolerant to Support Mixed-Mode
Low Static-Power Consumption Signal Operation
(ICC = 0.9 mA Maximum) • tpd = 5.9 ns Maximum at 3.3 V
Low Dynamic-Power Consumption Suitable for Point-to-Point Applications
(Cpd = 4.3 pF Typ at 3.3 V) Latch-Up Performance Exceeds 100 mA Per
Low Input Capacitance (Ci= 1.5 pF Typical) JESD 78, Class II
Low Noise – Overshoot and Undershoot ESD Performance Tested Per JESD 22
<10% of VCC 2000-V Human-Body Model
• Ioff Supports Partial-Power-Down Mode (A114-B, Class II)
Operation 1000-V Charged-Device Model (C101)
Wide Operating VCC Range of 0.8 V to 3.6 V
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS W
1
2
7
3
6
1A
1B
2Y
5
1Y
2B
2A
SN74AUP2G00
SCES752C –SEPTEMBER 2009REVISED MAY 2010
www.ti.com
The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP2G00YFPR _ _ _ H A _
0.23-mm Large Bump – YFP (Pb-free)
uQFN – DQE Reel of 5000 SN74AUP2G00DQER PN
–40°C to 85°C
QFN – RSE Reel of 5000 SN74AUP2G00RSER PN
SSOP – DCU Reel of 3000 SN74AUP2G00DCUR H00_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS OUTPUT
Y
A B
L L H
L X H
X L H
H H L
LOGIC DIAGRAM (POSITIVE LOGIC)
Pin number shown are for DCU and DQE packages.
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SCES752C –SEPTEMBER 2009REVISED MAY 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VIInput voltage range(2) –0.5 4.6 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VOOutput voltage range in the high or low state(2) 0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
DCU package 220
DQE package 261
qJA Package thermal impedance(3) °C/W
RSE package 253
YFP package 132
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
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SCES752C –SEPTEMBER 2009REVISED MAY 2010
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RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VCC = 0.8 V VCC
VCC = 1.1 V to 1.95 V 0.65 × VCC
VIH High-level input voltage V
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VCC = 0.8 V 0
VCC = 1.1 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VIInput voltage 0 3.6 V
VOOutput voltage 0 VCC V
VCC = 0.8 V –20 mA
VCC = 1.1 V –1.1
VCC = 1.4 V –1.7
IOH High-level output current VCC = 1.65 –1.9 mA
VCC = 2.3 V –3.1
VCC = 3 V –4
VCC = 0.8 V 20 mA
VCC = 1.1 V 1.1
VCC = 1.4 V 1.7
IOL Low-level output current VCC = 1.65 V 1.9 mA
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES752C –SEPTEMBER 2009REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA= 25°C TA= –40°C to 85°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX
IOH = –20 mA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1
IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.11 1.03
IOH = –1.9 mA 1.65 V 1.32 1.3
VOH V
IOH = –2.3 mA 2.05 1.97
2.3 V
IOH = –3.1 mA 1.9 1.85
IOH = –2.7 mA 2.72 2.67
3 V
IOH = –4 mA 2.6 2.55
IOL = 20 mA 0.8 V to 3.6 V 0.1 0.1
IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31 0.37
IOL = 1.9 mA 1.65 V 0.31 0.35
VOL V
IOL = 2.3 mA 0.31 0.33
2.3 V
IOL = 3.1 mA 0.44 0.45
IOL = 2.7 mA 0.31 0.33
3 V
IOL = 4 mA 0.44 0.45
IIA or B input VI= GND to 3.6 V 0 V to 3.6 V 0.1 0.5 mA
Ioff VIor VO= 0 V to 3.6 V 0 V 0.2 0.6 mA
ΔIoff VIor VO= 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 mA
VI= GND or (VCC to 3.6 V),
ICC 0.8 V to 3.6 V 0.5 0.9 mA
IO= 0
VI= VCC – 0.6 V(1),
ΔICC 3.3 V 40 50 mA
IO= 0
0 V 1.5
CiVI= VCC or GND pF
3.6 V 1.5
CoVO= GND 0 V 3 pF
(1) One input at VCC – 0.6 V, other input at VCC or GND
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 19.8
1.2 V ± 0.1 V 2.6 7.8 18.8 2.1 19.8
1.5 V ± 0.1 V 1.4 5.4 11.8 0.9 13.9
tpd A or B Y ns
1.8 V ± 0.15 V 1 4.3 9 0.5 11.1
2.5 V ± 0.2 V 1 3 5.9 0.5 7.8
3.3 V ± 0.3 V 1 2.4 4.9 0.5 5.9
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SCES752C –SEPTEMBER 2009REVISED MAY 2010
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 23.1
1.2 V ± 0.1 V 1.5 8.9 21.1 1 22
1.5 V ± 0.1 V 1 6.3 13.2 0.5 15.1
tpd A or B Y ns
1.8 V ± 0.15 V 1 5 10.1 0.5 12.2
2.5 V ± 0.2 V 1 3.6 7.4 0.5 9
3.3 V ± 0.3 V 1 2.9 5.2 0.5 6.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 24.7
1.2 V ± 0.1 V 3.6 9.8 21.7 3.1 22.7
1.5 V ± 0.1 V 2.3 4.6 14 1.8 15.7
tpd A or B Y ns
1.8 V ± 0.15 V 1.6 5.5 10.6 1.1 12.6
2.5 V ± 0.2 V 1 4 7 0.5 8.9
3.3 V ± 0.3 V 1 3.3 5.6 0.5 6.9
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 31.8
1.2 V ± 0.1 V 4.9 12.6 26.3 4.4 27
1.5 V ± 0.1 V 3.4 9 16.6 2.9 18.3
tpd A or B Y ns
1.8 V ± 0.15 V 2.5 7.3 12.9 2 14.8
2.5 V ± 0.2 V 1.8 5.4 8.8 1.3 10.5
3.3 V ± 0.3 V 1.5 4.5 6.7 1 8.2
OPERATING CHARACTERISTICS
TA= 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
0.8 V 4
1.2 V ± 0.1 V 4
1.5 V ± 0.1 V 4
Cpd Power dissipation capacitance f = 10 MHz pF
1.8 V ± 0.15 V 4
2.5 V ± 0.2 V 4.1
3.3 V ± 0.3 V 4.3
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l TEXAS INSTRUMENTS INVERTING AND NONINVEHTING OUTPUTS SETUP AND HOLD TIMES
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
1 M
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Output
VMVM
VMVM
VM
5, 10, 15, 30 pF
VCC/2
VCC
VCC = 1.2 V
±0.1 V
VCC = 0.8 V VCC = 1.5 V
±0.1 V
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
VCC = 3.3 V
±0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
CL
VM
VI
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
th
tsu
Data Input
Timing Input
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP2G00
www.ti.com
SCES752C –SEPTEMBER 2009REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , for
propagation delays tr/tf= 3 ns, for setup and hold times and pulse width tr/tf= 1.2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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l TEXAS INSTRUMENTS S1 Low- AND HIGH-LEVEL ENABLING
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
±0.1 V
VCC = 0.8 V VCC = 1.5 V
±0.1 V
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
VCC = 3.3 V
±0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 xVCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH - V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2xVCC
GND
TEST S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 k
5 k
2xVCC
SN74AUP2G00
SCES752C –SEPTEMBER 2009REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr/tf= 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPLH and tPHL are the same as tpd.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74AUP2G00DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 H00R
SN74AUP2G00DQER ACTIVE X2SON DQE 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 PN
SN74AUP2G00RSER ACTIVE UQFN RSE 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 PN
SN74AUP2G00YFPR ACTIVE DSBGA YFP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 HAN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AUP2G00 :
Automotive: SN74AUP2G00-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUP2G00DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AUP2G00DQER X2SON DQE 8 5000 180.0 8.4 1.2 1.6 0.55 4.0 8.0 Q1
SN74AUP2G00RSER UQFN RSE 8 5000 180.0 8.4 1.7 1.7 0.7 4.0 8.0 Q2
SN74AUP2G00YFPR DSBGA YFP 8 3000 178.0 9.2 0.9 1.75 0.6 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jan-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP2G00DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AUP2G00DQER X2SON DQE 8 5000 202.0 201.0 28.0
SN74AUP2G00RSER UQFN RSE 8 5000 202.0 201.0 28.0
SN74AUP2G00YFPR DSBGA YFP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jan-2020
Pack Materials-Page 2
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
I-I
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PACKAGE OUTLINE
C
1.05
0.95
1.45
1.35
0.40
0.34
0.05
0.00
2X 1.05
6X 0.35
7X 0.35
0.25
8X 0.20
0.15
0.45
0.35
(0.13) TYP
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
0.05 C
0.07 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package complies to JEDEC MO-287 variation X2EAF.
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
PIN 1 ID
SYMM
SYMM
1
45
8
SCALE 9.000
A
B
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EXAMPLE BOARD LAYOUT
6X (0.35)
(R0.05) TYP
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
7X (0.5)
8X (0.175)
(0.9)
(0.6)
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
SEE SOLDER MASK
DETAIL
1
45
8
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
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EXAMPLE STENCIL DESIGN
7X (0.5)
8X (0.175)
6X (0.35)
(0.9)
(R0.05) TYP
(0.6)
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 MM THICK STENCIL
SCALE: 40X
SYMM
SYMM
1
45
8
<3 i-iii="">
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PACKAGE OUTLINE
0.5 MAX
0.19
0.13
1.2
TYP
0.4 TYP
0.4 TYP
8X 0.25
0.21
0.30
0.25
E
D
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
0.05 C
A
12
0.015 C A B
SYMM
SYMM
B
C
D
SCALE 10.000
A
B
C
D: Max =
E: Max =
1.59 mm, Min =
0.79 mm, Min =
1.53 mm
0.73 mm
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EXAMPLE BOARD LAYOUT
0.05 MIN
0.05 MAX
8X ( 0.23) (0.4) TYP
(0.4) TYP
( 0.23)
SOLDER MASK
OPENING
( 0.23)
METAL
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
SOLDER MASK DETAILS
NOT TO SCALE
SYMM
SYMM
C
1 2
A
B
D
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
NON-SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(0.4) TYP
(0.4) TYP
8X ( 0.25) (R0.05) TYP
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
12
C
A
B
D
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
METAL
TYP
--I DJ]; 5771:7774 F \x““+‘ ‘w w 5®
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PACKAGE OUTLINE
C
0.6
0.5
0.05
0.00
2X
1
4X 0.5
6X 0.4
0.3
4X 0.3
0.2
2X 0.45
0.35
2X 0.25
0.15
2X 0.35
0.25
B1.55
1.45 A
1.55
1.45
(0.12)
TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
3
4
8
0.1 C A B
0.05 C
5
7
SYMM
SYMM
0.1 C A B
0.05 C
PIN 1 ID
(45 X 0.1)
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
0.1 C A B
0.05 C
SCALE 7.000
www.ti.com
EXAMPLE BOARD LAYOUT
2X (0.6)
2X (0.3)
2X
(0.2)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
6X (0.55)
4X (0.25)
4X (0.5)
(1.35)
(1.3)
(R0.05) TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
SYMM
1
35
8
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
4
7
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.55)
4X (0.25)
2X (0.6)
2X
(0.3)
(1.35)
(1.3)
2X (0.2)
4X (0.5)
(R0.05) TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
1
3
4
5
7
8
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE: 30X
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