SN65HVDA195-Q1 Datasheet by Texas Instruments

l V'.‘ TEXAS INSTRUMENTS
VSUP
INH
LIN
NWAKE
RXD
EN
TXD
Receiver
VSUP/2
Wake up
State
INH Control
Fault Detection
and Protection
Dominant State
Timeout
Filter
Driver with
Slope Control
Filter
30lQ
VSUP
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
SN65HVDA195-Q1 LIN and Most ECL Physical Interface
1 Features 3 Description
The SN65HVDA195 device is the Local Interconnect
1• LIN Physical Layer Specification Revision 2.0 Network (LIN) physical interface and MOST ECL
Compliant and Conforms to SAEJ2602 interface, which integrates the serial transceiver with
Recommended Practice for LIN wake-up and protection features. The bus is a single-
• LIN Bus Speed up to 20-kbps LIN Specified wire bidirectional bus typically used for low-speed in-
Maximum and MOST ECL Speeds Down to vehicle networks using data rates to 20 kbps. The
0 Baud device can transmit with an effective data rate of 0
kbps because it does not have dominant state time-
• Supports ISO9141 (K-Line) out. The protocol output data stream on TXD is
• Qualified for Automotive Applications converted by the SN65HVDA195 into the bus signal
• Sleep Mode: Ultra Low Current Consumption, through a current-limited wave-shaping driver as
Allows Wake-Up Events From LIN Bus, Wake-Up outlined by the LIN Physical Layer Specification
Input (External Switch), or Host Microcontroller Revision 2.0. The receiver converts the data stream
from the bus and outputs the data stream through
• High-Speed Receive Capable RXD. The bus has two states: dominant state
• ESD Protection to ±12 kV (Human Body Model) (voltage near ground) and the recessive state
on LIN Pin (voltage near battery). In the recessive state, the bus
• LIN Pin Handles Voltage From –40 V to 40 V is pulled high by the SN65HVDA195’s internal pullup
resistor and series diode, so no external pullup
• Survives Transient Damage in Automotive components are required for slave applications.
Environment (ISO 7637) Master applications require an external pullup resistor
• Extended Operation With Supply From 7 V to (1 kΩ) plus a series diode per the LIN specification.
27 V DC (LIN Specification 7 V to 18 V)
Device Information(1)
• Interfaces to Microcontroller With 5-V or 3.3-V I/O
Pins PART NUMBER PACKAGE BODY SIZE (NOM)
• Wake-Up Request on RXD Pin SN65HVDA195-Q1 SOIC (8) 4.90 mm × 3.91 mm
• Control of External Voltage Regulator (INH Pin) (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Integrated Pullup Resistor and Series Diode for
LIN Slave Applications Simplified Block Diagram
• Low Electromagnetic Emission (EME), High
Electromagnetic Immunity (EMI)
• Bus Terminal Short Circuit Protected for Short-to-
Battery or Short-to-Ground
• Thermally Protected
• Ground Disconnection Fail Safe at System Level
• Ground Shift Operation at System Level
• Unpowered Node Does Not Disturb the Network
2 Applications
• Automotive
• Industrial Sensing
• White Goods Distributed Control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
9.2 Functional Block Diagram....................................... 10
1 Features.................................................................. 19.3 Feature Description................................................. 10
2 Applications ........................................................... 19.4 Device Functional Modes........................................ 12
3 Description ............................................................. 110 Application and Implementation........................ 15
4 Revision History..................................................... 210.1 Application Information.......................................... 15
5 Description (continued)......................................... 310.2 Typical Application ............................................... 15
6 Pin Configuration and Functions......................... 311 Power Supply Recommendations ..................... 16
7 Specifications......................................................... 412 Layout................................................................... 17
7.1 Absolute Maximum Ratings ..................................... 412.1 Layout Guidelines ................................................. 17
7.2 ESD Ratings.............................................................. 412.2 Layout Example .................................................... 17
7.3 Recommended Operating Conditions....................... 413 Device and Documentation Support ................. 18
7.4 Thermal Information.................................................. 413.1 Community Resources.......................................... 18
7.5 Electrical Characteristics........................................... 513.2 Trademarks........................................................... 18
7.6 Typical Characteristics.............................................. 813.3 Electrostatic Discharge Caution............................ 18
8 Parameter Measurement Information .................. 913.4 Glossary................................................................ 18
9 Detailed Description............................................ 10 14 Mechanical, Packaging, and Orderable
9.1 Overview ................................................................. 10 Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2009) to Revision B Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Removed Ordering Information table .................................................................................................................................... 3
• Deleted Device Comparison table ....................................................................................................................................... 15
2Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS HHHH HHHH
1
2
3
45
6
7
8
GND
LIN
VSUP
INH
TXD
NWake
EN
RXD
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
5 Description (continued)
In sleep mode, the SN65HVDA195 requires low quiescent current even though the wake-up circuits remain
active, allowing for remote wake up through the LIN bus or local wake up through the NWake or EN pins.
The SN65HVDA195 has been designed for operation in the harsh automotive environment. The device can
handle LIN bus voltage swings from 40 V down to ground and survive –40 V. The device also prevents back-feed
current through LIN to the supply input, in case of a ground shift or supply voltage disconnection. It also features
undervoltage, overtemperature, and loss-of-ground protection. In the event of a fault condition, the output is
immediately switched off and remains off until the fault condition is removed.
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 RXD O RXD output (open drain) interface reporting state of LIN bus voltage
2 EN I Enable input
3 NWake I High voltage input for device wake up
4 TXD I TXD input interface to control state of LIN output
5 GND GND Ground
6 LIN I/O LIN bus single-wire transmitter and receiver
7 VSUP Supply Device supply voltage (connected to battery in series with external reverse blocking diode)
8 INH O Inhibit controls external voltage regulator with inhibit input
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
VSUP (2) Supply line supply voltage(3) 0 40 V
VNWake NWake DC and transient input voltage (through serial resistor) –0.3 40
NWake current if due to ground shifts VNWake ≤VGND – 0.3 V, thus the current into
INWake –3.6 mA
NWake must be limited through a serial resistance.
VINH INH voltage –0.3 VSUP + 0.3
VLogic_Input Logic pin input voltage RXD, TXD, EN –0.3 5.5 V
VLIN LIN DC-input voltage –40 40
TAOperational free-air temperature –40 125 °C
TJJunction temperature –40 150 °C
TSD Thermal shutdown 200 °C
TSD_HYS Thermal shutdown hysteresis 25 °C
Tstg Storage temperature –40 165 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) The device is specified for operation in the range of VSUP from 7 V to 27 V. Operating the device more than 27 V may significantly raise
the junction temperature of the device and system level thermal design must be considered.
7.2 ESD Ratings
VALUE UNIT
All pins except LIN and NWake ±4000
Human body model (HBM), per AEC Pin LIN ±12000
Q100-002(1)
Electrostatic
V(ESD) V
Pin NWake ±11000
discharge Charged-device model (CDM), per AEC All pins ±1500
Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VSUP 7 27 V
TAMB –40 125 °C
7.4 Thermal Information
SN65HVDA195-Q1
THERMAL METRIC(1) D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 112.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.3 °C/W
RθJB Junction-to-board thermal resistance 52.9 °C/W
ψJT Junction-to-top characterization parameter 19.3 °C/W
ψJB Junction-to-board characterization parameter 52.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
7.5 Electrical Characteristics
VSUP = 7 V to 27 V, TA= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY
Device is operational beyond the LIN 2.0 defined
Operational supply voltage(2) nominal supply line voltage range of 7 V ≤VSUP ≤7 14 27
18 V V
Normal and standby modes 7 14 18
Nominal supply line voltage Sleep mode 7 12 18
VSUP undervoltage threshold 4.8 6
Normal mode, EN = High, Bus dominant (total
bus load where RLIN ≥500 Ωand CLIN ≤10 nF 1.2 7.5
(see Figure 5)(3), INH = VSUP, NWake = VSUP mA
Standby mode, EN = low, Bus dominant (total
bus load where RLIN ≥500 Ωand CLIN ≤10 nF 1 2.1
(see Figure 5)(3), INH = VSUP, NWake = VSUP
Normal mode, EN = High, Bus recessive, 450 775
LIN = VSUP, INH = VSUP, NWake = VSUP
ISUP Supply current Standby mode, EN = Low, Bus recessive, 450 775
LIN = VSUP, INH = VSUP, NWake = VSUP
Sleep mode, EN = 0, TA= –40°C to 95°C,
7 V < VSUP ≤12 V, LIN = VSUP, 13 26
NWake = VSUP μA
Sleep mode, EN = 0, TA= –40°C to 95°C,
12 V < VSUP < 18 V, LIN = VSUP, 35
NWake = VSUP
Sleep mode, EN = 0, TA= –40°C to 95°C, Supply
Delta supply current in sleep line voltage range of
ΔISUP 20
mode 7 V ≤VSUP ≤18 V, LIN bus voltage: VSUP – 1.85
V≤LIN ≤VSUP
RXD OUTPUT PIN
VOOutput voltage –0.3 5.5 V
Low-level output current, open
IOL LIN = 0 V, RXD = 0.4 V 3.5 mA
drain
IIKG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 μA
TXD INPUT PIN
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.5
Input threshold hysteresis
VIT 30 500 mV
voltage
Pulldown resistor 125 350 800 kΩ
IIL Low-level input current TXD = Low –5 0 5 μA
LIN PIN (REFERENCED TO VSUP)
LIN recessive, TXD = High,
VOH High-level output voltage VSUP – 1
IO= 0 mA, VSUP = 14 V V
LIN dominant, TXD = Low,
VOL Low-level output voltage 0 0.2 × VSUP
IO= 40 mA, VSUP = 14 V
Rslave Pullup resistor to VSUP Normal and standby modes 20 30 60 kΩ
Pullup current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND –2 –20 μA
TXD = 0 V 45 160 220
ILLimiting current mA
TXD = 0 V, TA= –10°C to 125°C 200
(1) Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
(2) All voltages are defined with respect to ground; positive currents flow into the SN65HVDA195 device.
(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN slave termination
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN
slave termination is 20 kΩ, so the maximum supply current attributed to the termination is:
ISUP (dom) max termination ≉(VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
Electrical Characteristics (continued)
VSUP = 7 V to 27 V, TA= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
ILKG Leakage current LIN = VSUP –5 0 5
7 V < LIN ≤12 V, VSUP = GND 5 μA
Leakage current, loss of
ILKG supply 12 V < LIN < 18 V, VSUP = GND 10
VIL Low-level input voltage LIN dominant 0.4 × VSUP
VIH High-level input voltage LIN recessive 0.6 × VSUP
VIT Input threshold voltage 0.4 × VSUP 0.5 × VSUP 0.6 × VSUP V
0.05 × 0.175 ×
Vhys Hysteresis voltage VSUP VSUP
Low-level input voltage for
VIL 0.4 × VSUP
wakeup
EN PIN
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.5
Vhys Hysteresis voltage 30 500 mV
Pulldown resistor 125 350 800 kΩ
IIL Low-level input current EN = Low –5 0 5 μA
INH PIN
VoDC output voltage –0.3 VSUP + 0.3 V
Between VSUP and INH, INH = 2-mA drive,
Ron On state resistance 35 85 Ω
Normal or standby mode
IIKG Leakage current Low-power mode, 0 < INH < VSUP –5 0 5 μA
NWAKE PIN
VIL Low-level input voltage –0.3 VSUP – 3.3 V
VIH High-level input voltage VSUP – 1 VSUP + 0.3
Pullup current NWake = 0 V –45 –10 –2 μA
IIKG Leakage current VSUP = NWake –5 0 5
THERMAL SHUTDOWN
Shutdown junction thermal 190 °C
temperature
AC CHARACTERISTICS
THREC(max) = 0.744 × VSUP,
THDOM(max) = 0.581 × VSUP,
VSUP = 7 V to 18 V,
D1 Duty cycle 1(4) 0.396
tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT).
See Figure 1
THREC(min) = 0.422 × VSUP,
THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
D2 Duty cycle 2(4) 0.581
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT).
See Figure 1
THREC(max) = 0.778 × VSUP,
THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
D3 Duty cycle 3(4) 0.417
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT).
See Figure 1
(4) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The SN65HVDA195 also meets these lower data rate requirements, while it is capable of the higher
speed 20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty
cycle definitions, for details see the SAEJ2602 specification.
6Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
LIN Bus
Signal
DOMINANT
RECESSIVE D = 0.5
Thresholds:
Worst case 1
Thresholds:
Worst case 2
tBit tBit
Vsup
THRec(max)
THDom(max)
THRec(min)
THDom(min)
TXD (Input)
tBus_dom(max)
tBus_dom(min)
tBus_rec(max)
tBus_rec(min)
D = tBus_rec(min)/(2 x tBit)
D = tBus_rec(max)/(2 x tBit)
RXD
D2 (20 kbps) and
D4 (10 kbps) case
RXD
D1 (20 kbps) and
D3 (10 kbps) case
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
Electrical Characteristics (continued)
VSUP = 7 V to 27 V, TA= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
THREC(min) = 0.389 × VSUP,
THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
D4 Duty cycle 4(4) 0.59
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT).
See Figure 1
RRXD = 2.4 kΩ, CRXD = 20 pF
Receiver rising propagation
trx_pdr See Figure 2 6
delay time See Figure 5
RRXD = 2.4 kΩ, CRXD = 20 pF
Receiver falling propagation
trx_pdf See Figure 2 6
delay time See Figure 5
rising edge with respect to falling edge (trx_sym =
trx_pdf – trx_pdr)
Symmetry of receiver
trx_sym RRXD = 2.4 kΩ, CRXD = 20 pF –2 2 μs
propagation delay time See Figure 2
See Figure 5
NWake filter time for local
tNWake See Figure 9 25 50 150
wakeup
LIN wake-up filter time
tLINBUS (dominant time for wakeup See Figure 8 25 50 150
through LIN bus)
tgo_to_operate See Figure 7 to Figure 8 0.5 1
Figure 1. Definition of Bus Timing Parameters
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS v“
0
5
10
15
20
25
30
5 10 15 20 25 30
V
O
H
VSUP
VOHLIN -40°C
VOHLIN 25°C
VOHLIN 125°C
VOH
50% 50%
LIN Bus
RXD
0.4 VSUP
0.6 VSUP
VSUP
trx_pdf trx_pdr
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
Figure 2. Propagation Delay
7.6 Typical Characteristics
Figure 4. VSUP vs VOL
Figure 3. VSUP vs VOH
8Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS FE]
RXD
TXD
EN
NWake
INH
LIN
GND
CRXD
RRXD
VCC
VSUP
RLIN
CLIN
100 nF
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
8 Parameter Measurement Information
Figure 5. Test Circuit for AC Characteristics
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
VSUP
INH
LIN
GND
NWAKE
1
2
3
4
8
7
6
5
RXD
EN
TXD
Receiver
VSUP/2
Wake up
State
INH Control
Fault Detection
and Protection
Dominant State
Timeout
Filter
Driver with
Slope Control
Filter
30lQ
VSUP
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
9 Detailed Description
9.1 Overview
The SN65HVDA195-Q1 LIN transceiver is a LIN (Local Interconnect Network) physical layer transceiver which
integrates a serial transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional
bus that typically is used in low speed in vehicle networks with data rates that range from 2.4 kbps to 20 kbps
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Local Interconnect Network (LIN) Bus
This I/O pin is the single-wire LIN bus transmitter and receiver.
9.3.1.1 Transmitter Characteristics
The driver is a low-side transistor with internal current limitation and thermal shutdown. There is an internal 30-
kΩpullup resistor with a serial diode structure to VSUP, so no external pullup components are required for LIN
slave mode applications. An external pullup resistor of 1 kΩ, plus a series diode to VSUP must be added when the
device is used for master node applications.
Voltage on LIN can go from –40-V to 40-V DC without any currents other than through the pullup resistance.
There are no reverse currents from the LIN bus to supply (VSUP), even in the event of a ground shift or loss of
supply (VSUP).
The LIN thresholds and AC parameters are LIN Protocol Specification Revision 2.0 compliant.
During a thermal shut down condition, the driver is disabled.
9.3.1.2 Receiver Characteristics
The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,
with a hysteresis from 5% to 17.5% of supply.
The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the SN65HVDA195 to be used for high-speed downloads at end-of-line production or
other applications. The actual data rates achievable depend on system time constants (bus capacitance and
pullup resistance) and driver characteristics used in the system.
10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
Feature Description (continued)
9.3.2 Transmit Input (TXD)
TXD is the interface to the MCU’s LIN protocol controller or SCI/UART used to control the state of the LIN output.
When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is recessive (near
battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD has an internal
pulldown resistor. This device does not have a TXD dominant time-out protection circuit so that low data rates
may be used.
9.3.3 Receive Output (RXD)
RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus
voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is
represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the
SN65HVDA195 to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not
have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required.
9.3.3.1 RXD Wake-Up Request
When the SN65HVDA195 has been in low-power mode and encounters a wake-up event from the LIN bus or
NWake pin, RXD goes low, while the device enters and remains in standby mode (until EN is reasserted high
and the device enters normal mode).
9.3.4 Supply Voltage (VSUP)
VSUP is the SN65HVDA195 device power supply pin. VSUP is connected to the battery through an external
reverse battery blocking diode. The characterized operating voltage range for the SN65HVDA195 is from 7 V to
27 V. VSUP is protected for harsh automotive conditions up to 40 V.
The device contains a reset circuit to avoid false bus messages during undervoltage conditions when VSUP is less
than VSUP_UNDER.
9.3.5 Ground (GND)
GND is the SN65HVDA195 device ground connection. The SN65HVDA195 can operate with a ground shift as
long as the ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground
at the ECU level, the SN65HVDA195 does not have a significant current consumption on LIN bus.
9.3.6 Enable Input (EN)
EN controls the operation mode of the SN65HVDA195 (normal or sleep mode). When EN is high, the
SN65HVDA195 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN
is low the device is put into sleep mode and there are no transmission paths available. The device can enter
normal mode only after being woken up. EN has an internal pulldown resistor to ensure the device remains in
low-power mode even if EN floats.
9.3.7 NWake Input (NWake)
NWake is a high-voltage input used to wake up the SN65HVDA195 from low-power mode. NWake is usually
connected to an external switch in the application. A low on NWake that is asserted longer than the filter time
(tNWAKE) results in a local wakeup. NWake provides an internal pullup source to VSUP.
9.3.8 Inhibit Output (INH)
INH is used to control an external voltage regulator that has an inhibit input. When the SN65HVDA195 is in
normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator is activated.
When SN65HVDA195 is in low-power mode, the inhibit switch is turned off, which disables the voltage regulator.
A wake-up event on for the SN65HVDA195 returns INH to VSUP level. INH can also drive an external transistor
connected to an MCU interrupt input.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS V>V E _ high v st V>V N_Iow w. 5 VW. m ,u. mp m Driv an ax ow INH:H mom Telmina
Unpowered System
V V
sup sup_under
£
Standby Mode
Driver : Off
RXD: Low
INH: High (On)
Termination: 30 kW
EN = high
EN = low
EN = high
LIN Bus Wake-Up
or
Nwake Pin Wake-Up
V > V
EN = low
sup sup_under
V V
sup sup_under
£
V V
sup sup_under
£
V V
sup sup_under
£V > V
EN = high
sup sup_under
Sleep Mode
Driver : Off
RXD: Floating
INH: High impedance (Off)
Termination: Weak pullup
Normal Mode
Driver : On
RXD: LIN bus data
INH: High (On)
Termination: 30 kW
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
9.4 Device Functional Modes
9.4.1 Operating Modes
Figure 6. Operating States Diagram
Table 1. Operating Modes
LIN BUS
MODE EN RXD INH TRANSMITTER COMMENTS
TERMINATION
Sleep Low Floating Weak current pullup High impedance Off
Wake-up event detected, waiting
Standby Low Low 30 kΩ(typ) High Off on MCU to set EN
Normal High LIN bus data 30 kΩ(typ) High On LIN transmission up to 20 kbps
9.4.2 Normal Mode
This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to the
LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and
outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the
LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN
transitions high while the SN65HVDA195 is in sleep or standby mode.
9.4.3 Sleep Mode
Sleep mode is the power saving mode for the SN65HVDA195 and the default state after power up (assuming EN
is low during power up). Even with the extremely low current consumption in this mode, the SN65HVDA195 can
still wake up from LIN bus through a wake-up signal, a low on NWake, or if EN is set high. The LIN bus and
NWake are filtered to prevent false wake-up events. The wake-up events must be active for their respective time
periods (tLINBUS, tNWake).
12 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
‘5‘ TEXAS INSTRUMENTS 3W I 7,7,77,77,777777777777k, 7,7,77,77,777777777777k,
INH High Impedance
TXD
MODE Sleep Normal
EN
RXD Floating
LIN
t > tgo_to_operate
Vsup
Vsup
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
The sleep mode is entered by setting EN low.
While the device is in sleep mode, the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground). However, the weak current pullup is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• INH is high impedance.
• EN input, NWake input, and the LIN wake-up receiver are active.
9.4.4 Wake-Up Events
There are three ways to wake up the SN65HVDA195 from sleep mode:
• Remote wakeup through recessive (high) to dominant (low) state transition on LIN bus. The dominant state
must be held for tLINBUS filter time and then the bus must return to the recessive state (to eliminate false wake-
ups from disturbances on the LIN bus or if the bus is shorted to ground).
• Local wakeup through a low on NWake, which is asserted low longer than the filter time tNWake (to eliminate
false wake-ups from disturbances on NWake)
• Local wakeup through EN being set high
9.4.5 Standby Mode
This mode is entered whenever a wake-up event occurs through LIN bus or NWake while the SN65HVDA195 is
in sleep mode. The LIN bus slave termination circuit and INH are turned on when standby mode is entered. The
application system powers up once INH is turned on, assuming the system is using a voltage regulator
connected through INH. Standby mode is signaled through a low level on RXD.
When EN is set high while the SN65HVDA195 is in standby mode the device returns to normal mode and the
normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
Figure 7. Wakeup Through EN
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: SN65HVDA195-Q1
‘5‘ TEXAS INSTRUMENTS
NWake
INH High Impedance
EN
RXD Floating
TXD
MODE Sleep Normal
LIN
t > tgo_to_operate
Vsup
Vsup
t < tNWake
NWake VIL
NWake VIH
NWake VIL
Vsup
tNWake
Standby
LIN
INH High Impedance
EN
RXD Floating
TXD
MODE Sleep Standby Normal
Vsup
t > tgo_to_operate
Vsup
t < tLINBUS
0.4 × VSUP 0.4 V× SUP
0.6 V× SUP 0.6 V× SUP
tLINBUS
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
Figure 8. Wakeup Through LIN
Figure 9. Wakeup Through NWake
14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
‘5‘ TEXAS INSTRUMENTS :m z:
VBAT
VSUP
VDD
VDD
VSUP
INH
NWake
SN65HVDA195
MCU
MASTER
NODE
TMS470
LIN
Controller
or
SCI/UART(1)
EN
RXD
TXD
MCU w/o
pullup(2)
VDD I/O
GND
28 3 7
1
4 5
6
Master
Node
Pullup(3)
1 k
LIN
220 pF
VSUP
TPSxxxx
VSUP
VDD
VDD
VSUP
INH
NWake
SN65HVDA195
MCU
TMS470
LIN
Controller
or
SCI/UART(1)
EN
TXD
MCU w/o
pullup(2)
VDD I/O
GND
28 3 7
1
4 5
6
LIN
220 pF
RXD
SLAVE
NODE
LIN Bus
I/O
I/O
TPSxxxx
VSUP
VDD
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVDA195-Q1 can be used as both a slave device and a master device in a LIN network. It comes with
the ability to support both remote wake-up requests and local wake-up requests.
10.2 Typical Application
The device comes with an integrated 30-kΩpullup resistor and series diode for slave applications, and for master
applications an external 1-kΩpullup with series blocking diode can be used. Figure 10 shows the device being
used in both types of applications.
(1) RXD on MCU or LIN slave has internal pullup, no external pullup resistor is needed.
(2) RXD on MCU or LIN slave without internal pullup, requires external pullup resistor.
(3) Master node applications require an external 1-kΩpullup resistor and serial diode.
Figure 10. SN65HVDA195-Q1 Application Diagram
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS Tfik Run In my; Simple zuuv M 5.00»; c v I CIvCZ Dly mzsnus :2 mse Llanns usv Klulznls 071334 Tfik Run In my; Simple uuv zuuv CIvCZ Dly 5.9mm: c2 ran snuus Msnnu; : n z 6v Klulznls 0722 n
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
10.2.1 Design Requirements
For this design, use these requirements:
• RXD on MCU or LIN Slave has internal pullup, no external pullup resistor is needed.
• RXD on MCU or LIN Slave without internal pullup, requires external pullup resistor.
• Master Node applications require an external 1-kΩpullup resistor and serial diode
10.2.2 Detailed Design Procedure
The RXD output structure is an open-drain output stage. This allows the SN65HVDA195-Q1 to be used with 3.3-
V and 5-V I/O microcontrollers. If the RXD pin of the microcontroller does not have an integrated pullup, an
external pullup resistor to the microcontroller I/O supply voltage is equired.
The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the supply pin of the device
as possible.
The NWAKE pin is a high voltage wake-up input to the device. If this pin is not being used it should be tied to
VSUP.
10.2.3 Application Curves
Figure 11 and Figure 12 show the propagation delay from the TXD pin to the LIN pin for both the recessive to
dominant and dominant to recessive states under lightly loaded conditions.
Figure 11. SN65HVDA195-Q1 Dominant to Recessive Prop Figure 12. SN65HVDA195-Q1 Recessive to Dominant Prop
Delay Delay
11 Power Supply Recommendations
The SN65HVDSA195-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from
7 V to 27 V. A100-nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
16 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
1
2
3
4
U1
SN65HVDA195-Q1
8
7
6
5
C2
R3
R2
GND
EN
R6
R7 INH
D3
RXD
TXD
R1 C1
VC
R5
R4
VC
VSUP
GND
GND GND
D1
D2 R7
Only needed for
the master node
VSUP
C3
GND
SN65HVDA195-Q1
www.ti.com
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
12 Layout
12.1 Layout Guidelines
Pin 1 is the RXD output of the SN65HVDA195-Q1. It is an open-drain output and requires an external pullup
resistor in the range of 1-kΩto 10 kΩto function properly. If the micro-processor paired with the transceiver does
not have an integrated pullup and external resistor should be placed between RXD and the regulated voltage
supply for the micro-processor.
Pin 2 is the EN input pin for the device that is used to place the device in low power sleep mode. If this feature is
not used on the device, the pin should be pulled high to the regulated voltage supply of the
microprocessorthrough a series 1-kΩto 10-kΩseries resistor. Additionally, a series resistor may be placed on
the pin to limit the current on the digital lines in the case of a overvoltage fault.
Pin 3 is a high-voltage local wake up input pin. The device is typically externally controlled by a normally open
switch tied between NWAKE and ground. When the momentary switch is pressed the NWAKE pin is pulled to
ground signaling a local wake-up event. A series resistor between VBATT and the switch, and NWAKE and the
switch should be placed to limit current. If the NWAKE local wake-up feature is not used, the pin can be tied to
VSUP through a 1-kΩto 10-kΩpullup resistor.
Pin 4 is the transmit input signal to the device. A series resistor can be placed to limit the input current to the
device in the case of a overvoltage on this pin. Also a capacitor to ground can be placed close to the input pin of
the device to filter noise.
Pin 5 is the ground connection of the device. This pin should be tied to a ground plane through a short trace with
the use of two vias to limit total return inductance.
Pin 6 is the LIN bus connection of the device. For slave applications a 220-pF bus capacitor is implemented. For
master applications an additional series resistor and blocking diode should be placed between the LIN pin and
the VSUP pin.
Pin 7 is the supply pin for the device. A 100-nF decoupling capacitor should be placed as close to the device as
possible.
Pin 8 is a high-voltage output pin that may be used to control the local power supplies. If this feature is not used
the pin may be left floating.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
12.2 Layout Example
Figure 13. Layout Example
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: SN65HVDA195-Q1
l TEXAS INSTRUMENTS
SN65HVDA195-Q1
SLLS961B –JULY 2009–REVISED SEPTEMBER 2015
www.ti.com
13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVDA195-Q1
I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65HVDA195QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A195Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVDA195QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVDA195QDRQ1 SOIC D 8 2500 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated