NHD-0420CW-AW3 Datasheet by Newhaven Display Intl

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NHD-0420CW-AW3
Character OLED Display Module
NHD- Newhaven Display
0420- 4 Lines x 20 Characters
CW- Character OLED Module
A- Model
W- White
3- 2.4V~5.5V Supply Voltage
Newhaven Display International, Inc.
2661 Galvin Ct.
Elgin IL, 60124
Ph: 847-844-8795 Fax: 847-844-8796
www.newhavendisplay.com
nhtech@newhavendisplay.com nhsales@newhavendisplay.com
Document Revision History Revision Date Description Changed by 0 5/4/15 Initial Release AK 1 2/2/17 Thru-Hole Diameter Increased, Quality Table Updated, l2C SB Interface Updated
[2]
Document Revision History
Revision
Date
Description
Changed by
0
5/4/15
Initial Release
AK
1
2/2/17
Thru-Hole Diameter Increased, Quality Table Updated, I2C
Interface Updated
SB
Functions and Features
• 4 lines x 20 characters
• Built-in LCD comparable controller
• 4/8-bit Parallel, SPI, or I²C MPU interface
• 2.8V or 5.0V operation
• RoHS compliant
• Slim design
PROPRIETARY
1 2 3 4 5 6
A
B
C
D
B
C
D
1 2 3 4 5 6
Mechanical Drawing
A
[3]
The information contained herein is the exclusive property of Newhaven Display International, Inc. and shall not be copied, reproduced, and/or disclosed in any format without permission.
NHD-0420CW-AW3
02/02/17
Date
Unit
Part Number:
mm
Gen. Tol.
±0.3
Rev Description Date
Newhaven Display NHD-0420CW_RevB
Notes:
1. Emitting Color: White
2. Display format: 4 Lines x 20 Characters
3. Supply Voltage: 2.4V~5.5V
4. Interface: 4/8-bit Parallel, SPI, I²C
5. Controller: US2066
6. Recommended FFC Connector: MOLEX 52271-2079
p Parallel Interface: Pln Nn. Symbol External Connectlon Functlan Descrlptlon 1 VSS Power Supply Ground 2 V Power Supply Supply Voltage for OLED and Logic VDD:2,8V for 2.8V operation, VDD:5V for 5V operation 3 REGV Power Supply lnternal 5V I/O Regulator select signal REGVDD:OV for 2.8V operation, REGVDD:5V for 5V operation 4 D/C MPU Data/Command select signal. D/ : Command, D/C: : Data 5 R/w MPU Read/Write select signal, R/w . Read R/W:0: Write e E MPU Operation Enable signal Falling edge triggered. 740 DEO , DB3 MPU Four low order bicdirectional three-state data bus lines. These four are not used during 4-bit operation. 1144 DE4 , DB7 MPU Four high order [Ii-directional three-state data bus lines. 15 /C5 MPU Active LOW Chip Select signal 16 /RES MPU Active LOW Reset signal 1749 E50 7 E52 MPU MPU interface select signal 20 V55 Power Supply Ground Serial Interface: Pln Nn. Symbol External Connectlon Functlan Descrlptlon 1 VSS Power Supply Ground 2 V Power Supply Supply Voltage for OLED and Logic VDD:2,8V for 2.8V operation, VDD:5V for 5V operation 3 REGV Power Supply lnternal 5V I/O Regulator select signal REGVDD:OV for 2.8V operation, REGVDD:5V for 5V operation 46 NC . No Connect. Tie to Ground 7 SCLK MPU Serial Clock signal 8 SDI MPU Serial Data lnput signal 9 SDO MPU Serial Data Output signal 1044 NC . No Connect. Tie to Ground 15 /C5 MPU Active LOW Chip Select signal 16 /RES MPU Active LOW Reset signal 1749 E50 7 E52 MPU MPU interface select signal 20 V55 Power Supply Ground I‘C Interface: Pln Nn. Symbol External Connectlon Functlan Descrlptlon 1 VSS Power Supply Ground 2 V Power Supply Supply Voltage for OLED and Logic VDD:2.8V for 2.8V operation ONLV, 5V made not supported 3 REGV Power Supply lnternal 5V I/O Regulator select signal REGVDD:OV for 2.8V operation ONLV, 5V made not supported 4 5A0 MPU Slave Address select signal 56 NC . No Connect. Tie to Ground 7 5CL MPU Serial Clock signal 8 5DA MPU Serial Data lnput. 9 SDA MPU Serial Data Output. Tie togetherwith 5DA [pin 8) 1045 NC . No Connect. Tie to Ground 16 /RES MPU Active LOW Reset signal 1749 E50 7 E52 MPU MPU interface select signal 20 V55 Power Supply Ground
[4]
Pin Description
Parallel Interface:
Pin No.
External Connection
Function Description
1
Power Supply
Ground
2
DD
Power Supply
Supply Voltage for OLED and Logic
VDD=2.8V for 2.8V operation, VDD=5V for 5V operation
3
DD
Power Supply
Internal 5V I/O Regulator select signal
REGVDD=0V for 2.8V operation, REGVDD=5V for 5V operation
4
MPU
Data/Command select signal. D/C=0: Command, D/C=1: Data
5
MPU
Read/Write select signal, R/W=1: Read R/W=0: Write
6
MPU
Operation Enable signal. Falling edge triggered.
7-10
MPU
Four low order bi-directional three-state data bus lines.
These four are not used during 4-bit operation.
11-14
MPU
Four high order bi-directional three-state data bus lines.
15
MPU
Active LOW Chip Select signal
16
MPU
Active LOW Reset signal
17-19
MPU
MPU interface select signal
20
Power Supply
Ground
Serial Interface:
Pin No.
External Connection
Function Description
1
Power Supply
Ground
2
DD
Power Supply
Supply Voltage for OLED and Logic
VDD=2.8V for 2.8V operation, VDD=5V for 5V operation
3
DD
Power Supply
Internal 5V I/O Regulator select signal
REGVDD=0V for 2.8V operation, REGVDD=5V for 5V operation
4-6
-
No Connect. Tie to Ground
7
MPU
Serial Clock signal
8
MPU
Serial Data Input signal
9
MPU
Serial Data Output signal
10-14
-
No Connect. Tie to Ground
15
MPU
Active LOW Chip Select signal
16
MPU
Active LOW Reset signal
17-19
MPU
MPU interface select signal
20
Power Supply
Ground
I²C Interface:
Pin No.
External Connection
Function Description
1
Power Supply
Ground
2
DD
Power Supply
Supply Voltage for OLED and Logic
VDD=2.8V for 2.8V operation ONLY, 5V mode not supported
3
DD
Power Supply
Internal 5V I/O Regulator select signal
REGVDD=0V for 2.8V operation ONLY, 5V mode not supported
4
MPU
Slave Address select signal
5-6
-
No Connect. Tie to Ground
7
MPU
Serial Clock signal
8
MPU
Serial Data Input.
9
OUT
MPU
Serial Data Output. Tie together with SDA
IN
(pin 8)
10-15
-
No Connect. Tie to Ground
16
MPU
Active LOW Reset signal
17-19
MPU
MPU interface select signal
20
Power Supply
Ground
MPU Interface Pin Selections Pin 4—hlt Parallel 4—hlt Parallel a—hlt Parallel a—hlt Para||e| Serlal I‘c Name 6800 Interface 8080 Interface 6800 Interface 8080 Interface Interface Interface BSD 1 1 0 0 0 0 351 0 1 0 1 0 1 352 1 1 1 1 0 0 MPU Interface Pin Assignment Summary Bus Data/Command Interface Control Slgnals D7 I DG I 05 I D4 03 I 02 D1 00 E R/W /cs n/c [RES 4-bit 6800 D[7:4] Tie LOW E R/W /cs D/C /RES 4-bit 3030 D[7:4] Tie LOW /RD /WR /cs D/C /RES 8-bit 6800 D[7:0] E R/W /cs D/C /RES 8-bit 3030 D[7:0] /RD /WR /cs D/C /RES SPI Tie LOW SDO SDI SCLK Tie LOW /CS Tie LOW /RES I‘C Tie LOW SDA SDA SCL TIE LOW 5A0 /RES
[5]
MPU Interface Pin Selections
Pin
Name
4-bit Parallel
6800 interface
4-bit Parallel
8080 interface
8-bit Parallel
6800 interface
8-bit Parallel
8080 interface
Serial
Interface
I²C
Interface
BS0
1
1
0
0
0
0
BS1
0
1
0
1
0
1
BS2
1
1
1
1
0
0
MPU Interface Pin Assignment Summary
Bus
Interface
Data/Command Interface
Control Signals
D7
D6
D5
D4
D3
D2
D1
D0
E
R/W
/CS
D/C
/RES
4-bit 6800
D[7:4]
Tie LOW
E
R/W
/CS
D/C
/RES
4-bit 8080
D[7:4]
Tie LOW
/RD
/WR
/CS
D/C
/RES
8-bit 6800
D[7:0]
E
R/W
/CS
D/C
/RES
8-bit 8080
D[7:0]
/RD
/WR
/CS
D/C
/RES
SPI
Tie LOW
SDO
SDI
SCLK
Tie LOW
/CS
Tie LOW
/RES
I²C
Tie LOW
SDA
OUT
SDA
IN
SCL
Tie LOW
SA0
/RES
Electrical Characteristics Item Symbol candltlnn Mln. Typ. Max. Unlt Operating Temperature Range Tap Absolute Max -40 - +85 “c Storage Temperature Range 15, Absolute Max -40 - +90 “c Supply Voltage for logic VDD - 2.4 2.8 5.5 V Supply Voltage for l/o Regulator REGVDD VDD : 5V 4.4 5.0 5.5 V Supply Current lDD - - 70 135 mA Sleep Mode Current lDDSLEEP - - 2 5 mA “H“ Level input V.H - 0.8 * VDD - VDD V “L“ Level input V.L - VSS - 0.2 ‘ VDD V “H“ Level output VDH - 0.9 * VDD - VDD V “L“ Level output V0L - VSS - 0.1 ‘ VDD V Optical Characteristics Item Symbol Condltlon Min. Typ. Max. Unlt Top wV+ 80 - - ° Bottom ov- 80 - - ° Left 6X- 80 - - ° Right ex+ 80 - - ° Contrast Ratio CR - 10,000:1 - - - Rise TR - - 10 - us Fall TF - - 10 - us Brightness - 50% Checkerboard 80 100 - cd/m Lifetime - Tor: 25°C 50,000 - - Hrs. 50% Checkerboard No av e L C B P htt : www.newhavendis la .com a notes U52066. df DDRAM Address
[6]
Electrical Characteristics
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating Temperature Range
TOP
Absolute Max
-40
-
+85
⁰C
Storage Temperature Range
TST
Absolute Max
-40
-
+90
⁰C
Supply Voltage for logic
VDD
-
2.4
2.8
5.5
V
Supply Voltage for I/O Regulator
REGVDD
VDD = 5V
4.4
5.0
5.5
V
Supply Current
IDD
-
-
70
135
mA
Sleep Mode Current
IDDSLEEP
-
-
2
5
mA
“H” Level input
VIH
-
0.8 * VDD
-
VDD
V
“L” Level input
VIL
-
VSS
-
0.2 * VDD
V
“H” Level output
VOH
-
0.9 * VDD
-
VDD
V
“L” Level output
VOL
-
VSS
-
0.1 * VDD
V
Optical Characteristics
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Optimal
Viewing
Angles
Top
ϕY+
CR ≥ 10,000:1
80
-
-
⁰
Bottom
ϕY-
80
-
-
⁰
Left
θX-
80
-
-
⁰
Right
θX+
80
-
-
⁰
Contrast Ratio
CR
-
10,000:1
-
-
-
Response Time
Rise
TR
-
-
10
-
µs
Fall
TF
-
-
10
-
µs
Brightness
-
50% Checkerboard
80
100
-
cd/m2
Lifetime
-
T
OP
= 25°C
50% Checkerboard
50,000
-
-
Hrs.
Note: Lifetime at typical temperature is based on accelerated high-temperature operation. Lifetime is tested at
average 50% pixels on and is rated as Hours until Half-Brightness. The Display OFF command can be used to
extend the lifetime of the display.
Luminance of active pixels will degrade faster than inactive pixels. Residual (burn-in) images may occur. To avoid
this, every pixel should be illuminated uniformly.
Controller Information
Built-in US2066 controller.
Please download specification at http://www.newhavendisplay.com/app_notes/US2066.pdf
DDRAM Address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
Instruction Code R/w» (wnu)
[7]
Table of Commands
1. Fundamental Command List
Command IS RE SD
Instruction Code
Description
D/C#
R/W#
(WR#)
D7 D6 D5 D4 D3 D2 D1 D0
Clear Display X X 0 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM and set DDRAM
address to "00H" from AC.
Return Home X 0 0 0 0 0 0 0 0 0 0 1 *
Set DDRAM address to "00H" from AC and
return cursor to its original position if
shifted. The contents of DDRAM are not
changed.
Entry Mode
Set
X 0 0 0 0 0 0 0 0 0 1 I/D S
Assign cursor / blink moving direction
with DDRAM address.
I/D = "1": cursor/ blink moves to right and
DDRAM address is increased by 1 (POR)
I/D = "0": cursor/ blink moves to left and
DDRAM address is decreased by 1
Assign display shift with DDRAM address.
S = "1": make display shift of the enabled
lines by the DS4 to DS1 bits in the shift
enable instruction. Left/ right direction
depends on I/D bit selection.
S = "0": display shift disable (POR)
X 1 0 0 0 0 0 0 0 0 1 BDC BDS
Common bi-direction function.
BDC = "0": COM31 -> COM0
BDC = "1": COM0 -> COM31
Segment bi-direction function.
BDS = "0": SEG99 -> SEG0,
BDS = "1": SEG0 -> SEG99
Display ON/
OFF Control X 0 0 0 0 0 0 0 0 1 D C B
Set display/cursor/blink ON/OFF
D = "1": display ON,
D = "0": display OFF (POR),
C = "1": cursor ON,
C = "0": cursor OFF (POR),
B = "1": blink ON,
B = "0": blink OFF (POR).
Extended
Function Set X 1 0 0 0 0 0 0 0 1 FW BW NW
Assign font width, black/white inverting of
cursor, and 4line display mode control bit.
FW = "1": 6-dot font width,
FW = "0": 5-dot font width (POR),
B/W = "1": black/white inverting of cursor
enable,
B/W = "0": black/white inverting of cursor
disable (POR)
NW = "1": 3-line or 4-line display mode
NW = "0": 1-line or 2-line display mode
Instruction Code R/wu (wan) 5a cursor movmg and display smn R/L: “1" shrfltonght R/L: shmom
[8]
1. Fundamental Command Set
Command IS RE SD
Instruction Code
Description
D/C#
R/W#
(WR#)
D7 D6 D5 D4 D3 D2 D1 D0
Cursor or
Display Shift 0 0 0 0 0 0 0 0 1 S/C R/L * *
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left
Double
Height (4-
Line)/
Display-dot
Shift
0 1 0 0 0 0 0 0 1 UD2 UD1 * DH’
UD2~1: Assign different doubt height
format (POR=11b)
Refer to Table 7-2 for details
DH’ = "1": display shift enable
DH’ = "0": dot scroll enable (POR)
Shift Enable 1 1 0 0 0 0 0 0 1 DS4 DS3 DS2 DS1
DS[4:1]=1111b (POR) when DH’ = 1b
Determine the line for display shift.
DS1 = "1/0": 1st line display shift
enable/disable
DS2 = "1/0": 2nd line display shift
enable/disable
DS3 = "1/0": 3rd line display shift
enable/disable
DS4 = "1/0": 4th line display shift
enable/disable.
Scroll Enable 1 1 0 0 0 0 0 0 1 HS4 HS3 HS2 HS1
HS[4:1]=1111b (POR) when DH’ = 0b
Determine the line for horizontal
smooth scroll.
HS1 = "1/0": 1st line dot scroll
enable/disable
HS2 = "1/0": 2nd line dot scroll
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable.
Function Set
X 0 0 0 0 0 0 1 * N DH RE
(0) IS
Numbers of display line, N
when N = "1":
2-line (NW=0b) / 4-line (NW=1b),
when N = "0":
1-line (NW=0b) / 3-line (NW=1b)
DH = “ 1/0”: Double height font control
for 2-line mode enable/ disable (POR=0)
Extension register, RE ("0")
Extension register, IS
X 1 0 0 0 0 0 1 * N BE RE
(1) REV
CGRAM blink enable
BE = 1b: CGRAM blink enable
BE = 0b: CGRAM blink disable (POR)
Extension register, RE ("1")
Reverse bit
REV = "1": reverse display,
REV = "0": normal display (POR)
Instruction Code R/WN [wm Szlthe quanmy av nunmnm um 5cm“. (mama 0000) mm up (0 sa 5 m : llDODOb Instruction Code R/w» (wan) D 71 D 1 1 D 1 A[7,D] :oan, Dwsama intamal vDD [Egmatov at 5v I/o apphtaliun mcdz won) 0 72 D 1 1 1 0 0mm] 5219mm charactar nu althandevgenzratov 0mm. cam can 0] M M can 240 a cm 243 a 1017 250 5 1117 255 o no 12 mum mm 00!: A on: a on: c 11!: 1mm 0 73/79 0 1 1 0 SD Extansmn Registar, 50 59: ms so a
[9]
1. Fundamental Command Set
Command IS RE SD
Instruction Code
Description
D/C#
R/W#
(WR#)
D7 D6 D5 D4 D3 D2 D1 D0
Set CGRAM
Address 0 0 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
(POR=00 0000)
Set DDRAM
Address 0 0 0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.
(POR=000 0000)
Set Scroll
Quantity X 1 0 0 0 1 * SQ5 SQ4 SQ3 SQ2 SQ1 SQ0
Set the quantity of horizontal dot scroll.
(POR=00 0000)
Valid up to SQ[5:0] = 110000b
Read Busy
Flag and
Address/
Part ID
X X 0 0 1 BF
AC6
/
ID6
AC5
/
ID5
AC4
/
ID4
AC3
/
ID3
AC2
/
ID2
AC1
/
ID1
AC0
/
ID0
Can be known whether during internal
operation or not by reading BF. The
contents of address counter or the part
ID can also be read. When it is read the
first time, the address counter can be
read. When it is read the second time,
the part ID can be read.
BF = "1": busy state
BF = "0": ready state
Write Data X X 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM
(DDRAM / CGRAM).
Read Data X X 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM
(DDRAM / CGRAM).
2. Extended Command Set
Command IS RE SD
Instruction Code
Description
D/C#
R/W#
(WR#)
Hex D7 D6 D5 D4 D3 D2 D1 D0
Function
Selection A
X
X
1
1
0
0
0
1
0
0
71
A[7:0]
0
A7
1
A6
1
A5
1
A4
0
A3
0
A2
0
A1
1
A0
A[7:0] = 00h, Disable internal
VDD regulator at 5V I/O
application mode
A[7:0] = 5Ch, Enable internal
VDD regulator at 5V I/O
application mode (POR)
Function
Selection B
X
X
1
1
0
0
0
1
0
0
72
0
*
1
*
1
*
1
*
0
ROM
1
0
ROM
0
1
OPR
1
0
OPR
0
OPR[1:0]: Select the character
no. of character generator
OPR[1:
0]
CGRO
M
CGRA
M
00b
240
8
01b
248
8
10b
250
6
11b
256
0
ROM[1:0]: Select character
ROM
RO[1:0]
ROM
00b
A
01b
B
01b
C
11b
Invalid
OLED
Characteriza
tion
X
1
X
0
0
78/79
0
1
1
1
1
0
0
SD
Extension Register, SD
SD=0b: OLED Command set is
disabled (POR)
SD=1b: OLED Command set is
enabled.
Instruction Code n/wu (wan) D 81 1 D o o o o D 1 Dunb‘e hmemmmandm 0 D5 1 1 n 1 n 1 D 1 mm: Denneme mwdemm (a) uhhe disp‘a clack 19cm :1 m' mam] « (PDR comm 52! me Oscillat Frequency, ro Oscillatur rre mcreases w. vame or A[7 vice versa, (PDR=D]1]h| Rangemooh-nnn equency increases as s vame mereases. 0 D9 1 1 D 1 1 n n 1 mm: Phase 1 peviud of up to 31 DCLK, (Inc an valid entry w DCLK (PO 0 Phase 2 pena m 15 DCLK, ( mvalid entry (PDR=0]1]h| 0 DE 1 1 u 1 1 u 1 1 A[6:4] Hex 33"? aooh Dan was x Vt: 0011a mn ~a,71 x Vt: 0103 20h ~a,77 x Vt: (FDR) 011 ion was x Vt: mob nan 1XV:(
[10]
3. OLED Command Set
Command IS RE SD
Instruction Code
Description
D/C
#
R/W#
(WR#)
Hex D7 D6 D5 D4 D3 D2 D1 D0
Set Contrast
Control
X
X
1
1
1
1
0
0
0
0
81
A[7:0]
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
1
A0
Double byte command to
select 1 out of 256 contrast
steps. Contrast increases as
the value increases.
(POR = 7Fh )
Set Display
Clock Divide
Ratio /
Oscillator
Frequency
X
X
1
1
1
1
0
0
0
0
D5
A[7:0]
1
A7
1
A6
0
A5
1
A4
0
A3
1
A2
0
A1
1
A0
A[3:0]: Define the divide ratio
{D) of the display
clocks (DCLK) divide
ratio = A[3:0] + 1
(POR=0000b)
A[7:4]: Set the Oscillator
Frequency, FOSC.
Oscillator Frequency
increases with the
value of A[7:4] and
vice versa.
(POR=0111b)
Range:0000b~1111b
Frequency increases as setting
value increases.
Set Phase
Length
X
X
1
1
1
1
0
0
0
0
D9
A[7:0]
1
A7
1
A6
0
A5
1
A4
1
A3
0
A2
0
A1
1
A0
A[3:0]: Phase 1 period of up
to 32 DCLK; clock 0 is
an valid entry with 2
DCLK (POR=1000b)
A[7:4]: Phase 2 period of up
to 15 DCLK; clock 0 is
invalid entry
(POR=0111b)
Set SEG Pins
Hardware
Configuration
X
X
1
1
1
1
0
0
0
0
DB
A[6:4]
1
0
1
A6
0
A5
1
A4
1
0
0
0
1
0
1
0
A[6:4]
Hex
Code
V
COMH
Deselect
level
000b
00h
~0.65 x
VCC
001b
10h
~0.71 x
VCC
010B
20h
~0.77 x
VCC
(POR)
011
30h
~0.83 x
VCC
100b
40h
1 x VCC
Instruction Code AlSA] = can Disable rm om TImE interval a: a Frames 16 Frames 1:: Frames
[11]
1. OLED Command Set
Command IS RE SD
Instruction Code
Description
D/C
#
R/W#
(WR#)
Hex D7 D6 D5 D4 D3 D2 D1 D0
Function
Selection C
X
X
1
1
1
1
0
0
0
0
DC
A[7:0]
1
A7
1
A6
0
A5
1
A4
1
A3
1
A2
0
A1
0
A0
Set VSL & GPIO
Set VSL:
A[7] = 0b: Internal VSL (POR)
A[7] = 1b: Enable external VSL
Set GPIO:
A[1:0]= 00b represents GPIO
pin HiZ, input disabled
(always read as low)
A[1:0]= 01b represents GPIO
pin HiZ, input enabled
A[1:0]= 10b represents GPIO
pin output Low (RESET)
A[1:0]= 11b represents GPIO
pin output High
Set Fade Out
and Blinking
X
X
1
1
1
1
0
0
0
0
23
A[5:0]
0
*
0
*
1
A5
0
A4
0
A3
0
A2
1
A1
1
A0
A[5:4] = 00b Disable Fade Out
/ Blinking Mode[RESET]
A[5:4] = 10b Enable Fade Out
mode. Once Fade Mode is
enabled, contrast decrease
gradually to all pixels OFF.
Output follows RAM content
when Fade mode is disabled.
A[5:4] = 11b Enable Blinking
mode. Once Blinking Mode is
enabled, contrast decrease
gradually to all pixels OFF and
then contrast increases
gradually to normal display.
This process loops
continuously until the Blinking
mode is disabled.
A[3:0] : Set time interval for
each fade step
A[3:0]
Time interval of
for each fade
step
0000b
8 Frames
0001b
16 Frames
0010b
24 Frames
:
:
1110b
120 Frames
1111b
128 Frames
T 6800-Series Parallel Interface: Symbol Parameter Min Unit (K (.2 Clock Cycle Time (wrlte cyclel 400 ns tAS Address Setup Time 13 ns tAH Address Hold Time 17 ns tCS cmp Select Time 0 ns tCH cmp Select Hald Time 0 ns tDSW Write Data Setup Tlme 35 ns tDHW Write Data Hald Time 18 ns tw Read Data Hald Time 13 ns tON Output Dlsable Tlme 10 ns t Access Tlme lRAM) Access Tlme Icammand) PW cmp Select Law Pulse Width lread MW 250 ns Chlp Select Law Pulse Width [read C0 250 ns cmp Select Law Pulse Width lwrite) 50 ns PW cmp Select High Pulse Width (readl 155 ns cmp Select High Pulse Width (wrltel 55 ns tW Rise Time - ns I; Fall Tlme - ns C D/C# tAS R/W# C W6" 3 4 '11: CS# \ tnj 7 D[7:0] (Write) Valid Data tAcc D[7:0] (Read) —‘—3
[12]
Timing Characteristics
6800-Series Parallel Interface:
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle Time (write cycle)
400
-
-
ns
tAS
Address Setup Time
13
-
-
ns
tAH
Address Hold Time
17
-
-
ns
tCS
Chip Select Time
0
-
-
ns
tCH
Chip Select Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
35
-
-
ns
tDHW
Write Data Hold Time
18
-
-
ns
tDHR
Read Data Hold Time
13
-
-
ns
tOH
Output Disable Time
10
-
90
ns
t
ACC
Access Time (RAM)
Access Time (command)
- - 125 ns
PW
CSL
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
250
250
50
-
-
-
-
-
-
ns
ns
ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
155
55
-
-
-
-
ns
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
Condition 1: /CS low pulse width > E high pulse width
D/C# t“ t»! R/W# t5 tCH CS# PWcsn /E PWLSL ‘ tmic j E tn—N —>\ [:t; ; tusw tmw D[7:0] (Write) Valid Data tmiu tacc D[7:0] (Read) ——‘—3 Valid Data tori
[13]
Condition 2: /CS low pulse width < E high pulse width
8080-Series Parallel Interface: Symbol Parameter Min Typ Max Unit twee Clock Cycle Time (wrlte cyclel 400 - - ns tAS Address Setup Time 13 - - ns tAH Address Hold Time 17 - - ns tCS cmp Select Time 0 - - ns 1C5” cmp Select hold time to read signal 0 - - ns tDSW Write Data Setup Tlme 35 - - ns tDHW Write Data Hold Time 18 - - ns tw Read Data Hold Time 13 - - ns tON Output Dlsable Tlme 10 - 70 ns t Access Tlme lRAM) Access Tlme Icommand) PW cmp Select Low Pulse Width lread RAMl - tv 250 - - ns Chlp Select Low Pulse Width [read Com n 250 - - ns cmp Select Low Pulse Width lwrite) - tPWLW 50 - - ns PW cmp Select High Pulse Width (readl - tP 15S - - ns cmp Select High Pulse Width (wrltel «NW 55 - - ns tW Rise Time - - 15 ns tF Fall TlmE - - 15 ns ('S= D (‘7- \VR= UL: D[7 0]
[14]
8080-Series Parallel Interface:
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle Time (write cycle)
400
-
-
ns
tAS
Address Setup Time
13
-
-
ns
tAH
Address Hold Time
17
-
-
ns
tCS
Chip Select Time
0
-
-
ns
tCSH
Chip Select hold time to read signal
0
-
-
ns
tDSW
Write Data Setup Time
35
-
-
ns
tDHW
Write Data Hold Time
18
-
-
ns
tDHR
Read Data Hold Time
13
-
-
ns
tOH
Output Disable Time
10
-
70
ns
t
ACC
Access Time (RAM)
Access Time (command)
- - 125 ns
PW
CSL
Chip Select Low Pulse Width (read RAM) - t
PWLR
Chip Select Low Pulse Width (read Command) - tPWLR
Chip Select Low Pulse Width (write) - tPWLW
250
250
50
-
-
-
-
-
-
ns
ns
ns
PW
CSH
Chip Select High Pulse Width (read) - t
PWHR
Chip Select High Pulse Width (write) - tPWHW
155
55
-
-
-
-
ns
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
Serial Interface: Symbol Parameter Min Typ Max Unit tC Serial Clock Cycle Tlme 1 - 20 us (p, tF Serial clock rise/tall time - - 15 ns tW Serial clock width (high, Iowl 400 - - as [5“] Chip select setup time so - - ns tm Chip select hold time 20 - - ns tsuz Serial input data setup time 200 - - as (M Serial input data hold time TBD - - ns tD Serial output data delay time - - TED ns tm. Serial output data hold time 10 - 70 ns (3}! VlLl tsul r tR l Vim SCLK Viu tsuZ SID to tan SOD ch Vou
[15]
Serial Interface:
Symbol
Parameter
Min
Typ
Max
Unit
tC
Serial Clock Cycle Time
1
-
20
µs
tR, tF
Serial clock rise/fall time
-
-
15
ns
tW
Serial clock width (high, low)
400
-
-
ns
tsu1
Chip select setup time
60
-
-
ns
th1
Chip select hold time
20
-
-
ns
tsu2
Serial input data setup time
200
-
-
ns
th2
Serial input data hold time
TBD
-
-
ns
tD
Serial output data delay time
-
-
TBD
ns
tDH
Serial output data hold time
10
-
70
ns
IzC Interface: Symbol Parameter Min Typ Max Unit (tyne Clock Cycle Time 2.5 - - ps 5mm Start Condition Hold Time 0.5 - - ps tMD Data Hoid Time (for “50AM" pini 5 - - ns Data Hoid Time (for ”SDAW" pm) 300 - - ns tSD Data Setup Time 100 - - ns gm, Start condition setup time (Oniy for a repeated Start Condition) 0.5 - - ps teem Stop condition Setup Time 0.5 - - ps I" Rise Time for data and clock pin - - 300 ns t; Fail Time for data and Clock pin - - 300 ns (rm IdieTime before a new transmission can start 1.3 - - p5 ________ H. - _ _ - _ _ - - SDA r tIDLE .— nim n _. t)” term CW SCL H
[16]
I²C Interface:
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle Time
2.5
-
-
µs
tHSTART
Start Condition Hold Time
0.6
-
-
µs
tHD
Data Hold Time (for “SDAOUT” pin)
5
-
-
ns
Data Hold Time (for “SDAIN” pin)
300
-
-
ns
tSD
Data Setup Time
100
-
-
ns
tSSTART
Start condition setup time (Only for a repeated Start Condition)
0.6
-
-
µs
tSSTOP
Stop condition Setup Time
0.6
-
-
µs
tR
Rise Time for data and clock pin
-
-
300
ns
tF
Fall Time for data and clock pin
-
-
300
ns
tIDLE
Idle Time before a new transmission can start
1.3
-
-
µS
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[17]
Built-in Font Tables
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[18]
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[19]
[20]
Example Program Code
void command(char i)
{
C_S = 0; //chip select LOW – active
P1 = i; //data on port
D_C = 0; //data/command select LOW – command
R_W = 0; //read/write select LOW – write
E = 1; //enable HIGH
delayms(1); //delay
E = 0; //enable LOW – data latched
}
void data(char i)
{
C_S = 0; //chip select LOW – active
P1 = i; //data on port
D_C = 1; //data/command select HIGH – data
R_W = 0; //read/write select LOW – write
E = 1; //enable HIGH
delayms(1); //delay
E = 0; //enable LOW – data latched
}
void output()
{
int i;
command(0x01); //clear display
command(0x02); //return home
for(i=0;i<20;i++)
{
data(0x1F); //write solid blocks
}
command(0xA0); //line 2
for(i=0;i<20;i++)
{
data(0x1F); //write solid blocks
}
command(0xC0); //line 3
for(i=0;i<20;i++)
{
data(0x1F); //write solid blocks
}
command(0xE0); //line 4
for(i=0;i<20;i++)
{
data(0x1F); //write solid blocks
}
}
[21]
void init()
{
RES = 1; //reset HIGH – inactive
delayms(1); //delay
command(0x2A); //function set (extended command set)
command(0x71); //function selection A
data(0x00); // disable internal VDD regulator (2.8V I/O). data(0x5C) = enable regulator (5V I/O)
command(0x28); //function set (fundamental command set)
command(0x08); //display off, cursor off, blink off
command(0x2A); //function set (extended command set)
command(0x79); //OLED command set enabled
command(0xD5); //set display clock divide ratio/oscillator frequency
command(0x70); //set display clock divide ratio/oscillator frequency
command(0x78); //OLED command set disabled
command(0x09); //extended function set (4-lines)
command(0x06); //COM SEG direction
command(0x72); //function selection B
data(0x00); //ROM CGRAM selection
command(0x2A); //function set (extended command set)
command(0x79); //OLED command set enabled
command(0xDA); //set SEG pins hardware configuration
command(0x10); //set SEG pins hardware configuration
command(0xDC); //function selection C
command(0x00); //function selection C
command(0x81); //set contrast control
command(0x7F); //set contrast control
command(0xD9); //set phase length
command(0xF1); //set phase length
command(0xDB); //set VCOMH deselect level
command(0x40); //set VCOMH deselect level
command(0x78); //OLED command set disabled
command(0x28); //function set (fundamental command set)
command(0x01); //clear display
command(0x80); //set DDRAM address to 0x00
command(0x0C); //display ON
delayms(100); //delay
}
void main(void)
{
init();
while(1)
{
output();
delayms(2000);
}
}
Quality Information Test Item Content of Test Test Condition Note High Temperature Test the endurance ofthe display at +90%, 240hrs 2 storage high storage temperature. Low Temperature Test the endurance of the display at 740°C, 240hrs 1,2 storage low storage temperature. High Temperature Test the endurance ofthe display by +85"C 240hrs 2 applying electric stress lvoltag current) at high temperature. Low Temperature Test the endurance of the display by 740°C, 240hrs 1,2 applying electric stress lvoltag current) at low temperature. High Temperature/ Test the endurance ofthe display by +60"C, 90% RH, 240hrs 1,2 applying el current) at humidity. Thermal Shock Test the endurance ofthe display by 740°C,30min ,> 25”C,Smin ,> applying electric current) during temperatures. Vibration test Test the endurance ofthe display by 10*22Hz, 1.5mm amplitude. 3 22*500HZ, 1.SG 30min in each 0 directions X,Y,Z Static electricity test Test the endurance ofthe display by V5=800V, R =1.5kQ, C5=100pF One time Not Not No Ev 1 2 3 4 P for using OLEDs/LCDs/LCMs S www.newhavendisplaycomlspecsflzrecautionspdf Warranty Information and Terms & Conditio http: /www.newhavendisplav.com index.php?main page=terms
[22]
Quality Information
Test Item
Content of Test
Test Condition
Note
High Temperature
storage
Test the endurance of the display at
high storage temperature.
+90⁰C , 240hrs
2
Low Temperature
storage
Test the endurance of the display at
low storage temperature.
-40⁰C , 240hrs
1,2
High Temperature
Operation
Test the endurance of the display by
applying electric stress (voltage &
current) at high temperature.
+85⁰C 240hrs
2
Low Temperature
Operation
Test the endurance of the display by
applying electric stress (voltage &
current) at low temperature.
-40⁰C , 240hrs
1,2
High Temperature /
Humidity Operation
Test the endurance of the display by
applying electric stress (voltage &
current) at high temperature with high
humidity.
+60⁰C , 90% RH , 240hrs
1,2
Thermal Shock
resistance
Test the endurance of the display by
applying electric stress (voltage &
current) during a cycle of low and high
temperatures.
-40⁰C,30min -> 25⁰C,5min ->
85⁰C,30min = 1 cycle
100 cycles
Vibration test
Test the endurance of the display by
applying vibration to simulate
transportation and use.
10-22Hz , 1.5mm amplitude.
22-500Hz, 1.5G
30min in each of 3
directions X,Y,Z
3
Static electricity test
Test the endurance of the display by
applying electric static discharge.
V
S
=800V, R
S
=1.5kΩ,
CS=100pF
One time
Note 1: No condensation to be observed.
Note 2: Conducted after 2 hours of storage at 25⁰C, 0%RH.
Note 3: Test performed on product itself, not inside a container.
Evaluation Criteria:
1: Display is fully functional during operational tests and after all tests, at room temperature.
2: No observable defects.
3: Luminance >50% of initial value.
4: Current consumption within 50% of initial value
Precautions for using OLEDs/LCDs/LCMs
See Precautions at www.newhavendisplay.com/specs/precautions.pdf
Warranty Information and Terms & Conditions
http://www.newhavendisplay.com/index.php?main_page=terms