TLV3401,02,04 Datasheet by Texas Instruments

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TLV340x mP

1 MW

100 kW

1 MW

VREF

VCC

700

600

500

400

300

200

100

0 2 46 8 10 12 14 16

Supply Voltage (V)

Supply Current (nA)

T = 125 C

A°

V = 1 V

ID -

T = 25 C

A°

T = 0 C

A°

T = 40 C

A- °

T = 70 C

A°

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

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Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV3401

TLV3402

TLV3404

SLCS135B –AUGUST 2000–REVISED JANUARY 2017

TLV340x Family of Nanopower, Open-Drain Output Comparators

1 Features

1• Low Supply Current: 470 nA Per Channel

• Input Common-Mode Range Exceeds the Rails:

–0.1 V to VCC +5V

• Supply Voltage Range: 2.5 V to 16 V

• Reverse Battery Protection Up to 18 V

• Open-Drain CMOS Output Stage

• Specified Temperature Range:

– Commercial Grade: 0°C to +70°C

– Industrial Grade: –40°C to +125°C

• Ultra-Small Packaging:

– 5-Pin SOT-23 (TLV3401)

– 8-Pin MSOP (TLV3402)

• Universal Op Amp EVM (See Universal

Operational Amplifier Evaluation Module Selection

Guide For More Information)

2 Applications

• Portable Medical Equipment

• Wireless Security Systems

• Remote Control Systems

• Handheld Instruments

• Ultra-Low Power Systems

Supply Current vs Supply Voltage

3 Description

The TLV340x is TI's first family of nanopower

comparators with only 470 nA per channel supply

current, which makes this device ideal for battery-

powered and wireless handset applications.

The TLV340x has a minimum operating supply

voltage of 2.7 V over the extended industrial

temperature range (TA= –40°C to +125°C), while

having an input common-mode range of –0.1 to

VCC + 5 V. The low supply current makes it an ideal

choice for battery-powered portable applications

where quiescent current is the primary concern.

Reverse battery protection guards the amplifier from

an overcurrent condition due to improper battery

installation. For harsh environments, the inputs can

be taken 5 V above the positive supply rail without

damage to the device.

All members are available in PDIP and SOIC with the

single versions in the small SOT-23 package, dual

versions in the VSSOP package, and quad versions

in the TSSOP package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TLV3401 SOT-23 (5) 2.90 mm × 1.60 mm

TLV3401, TLV3402 SOIC (8) 4.90 mm × 3.91 mm

TLV3401, TLV3402 PDIP (8) 9.81 mm × 6.35 mm

TLV3402 VSSOP (8) 3.00 mm × 3.00 mm

TLV3404

SOIC (14) 8.65 mm × 3.91 mm

TSSOP (14) 5.00 mm × 4.40 mm

PDIP (14) 19.30 mm × 6.35 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

High-Side Voltage Sense Circuit

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information: TLV3401 ................................. 7

7.5 Thermal Information: TLV3402 ................................. 7

7.6 Thermal Information: TLV3404 ................................. 7

7.7 Electrical Characteristics........................................... 8

7.8 Switching Characteristics.......................................... 8

7.9 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram....................................... 12

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 12

9 Application and Implementation ........................ 13

9.1 Application Information............................................ 13

9.2 Typical Application ................................................. 13

10 Power Supply Recommendations ..................... 15

11 Layout................................................................... 15

11.1 Layout Guidelines ................................................. 15

11.2 Layout Example .................................................... 15

12 Device and Documentation Support ................. 16

12.1 Device Support...................................................... 16

12.2 Documentation Support ........................................ 16

12.3 Related Links ........................................................ 16

12.4 Receiving Notification of Documentation Updates 16

12.5 Community Resource............................................ 17

12.6 Trademarks........................................................... 17

12.7 Electrostatic Discharge Caution............................ 17

12.8 Glossary................................................................ 17

13 Mechanical, Packaging, and Orderable

Information ........................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2000) to Revision B Page

• Added ESD Rating table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section; ................................................................................................ 1

• Deleted Available Options tables; refer to Package Option Addendum at the end of this data sheet................................... 3

• Deleted Dissipation Ratings table........................................................................................................................................... 6

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(1) All specifications are typical values measured at 5 V.

5 Device Comparison Table

DEVICE(1) VCC (V) VIO (µV) ICC/Ch

(µA) IIB (pA) tPLH (µs) tPHL (µs) tF(µs) tR(µs) RAIL-TO-

RAIL OUTPUT

STAGE

TLV340x 2.5 to 16 250 0.47 80 55 30 5 — Input OD

TLV370x 2.5 to 16 250 0.47 80 25 30 5 3.5 Input PP

TLC3702/4 3 to 16 1200 9 5 1.1 0.65 0.5 0.125 — PP

TLC393/339 3 to 16 1400 11 5 1.1 0.55 0.22 — — OD

TLC372/4 3 to 16 1000 75 5 0.65 0.65 — — — OD

*9 TEXAS INSTRUMENTS III: III:

1OUT

1IN-

1IN+

GND

2OUT

2IN-

2IN+

VCC

OUT

GND

IN+ IN-

VCC

IN-

IN+

GND

OUT

VCC

TLV3401

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TLV3404

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6 Pin Configuration and Functions

TLV3401: DBV Package

5-Pin SOT-23

Top View

TLV3401: D and P Packages

8-Pin SOIC and VSSOP

Top View

Pin Functions: TLV3401

I/O DESCRIPTION

NAME TLV3401

SOT-23 SOIC, PDIP

GND 2 4 — Ground

IN– 4 2 I Negative (inverting) input

IN+ 3 3 I Positive (noninverting) input

NC — 1, 5, 8 — No internal connection (can be left floating)

OUT 1 6 O Output

VCC 5 7 — Positive power supply

TLV3402: D, DGK, and P Packages

8-PIN SOIC, PDIP, and VSSOP

Top View

Pin Functions: TLV3402

I/O DESCRIPTION

NAME

TLV3402

SOIC, PDIP,

VSSOP

GND 4 — Ground

1IN– 2 I Inverting input, channel 1

2IN– 6 I Inverting input, channel 2

1IN+ 3 I Noninverting input, channel 1

2IN+ 5 I Noninverting input, channel 2

1OUT 1 O Output, channel 1

2OUT 7 O Output, channel 2

VCC 8 — Positive power supply

l TEXAS INSTRUMENTS UT %6 9% HHHHHHH HHHHHHH UT

1OUT

1IN-

1IN+

2IN+

2IN-

2OUT

4OUT

4IN-

4IN+

GND

3IN+

3IN-

3OUT

VCC

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TLV3404: D, N, and PW Packages

14-PIN SOIC, PDIP, TSSOP

Top View

Pin Functions: TLV3404

I/O DESCRIPTION

NAME

TLV3404

SOIC, PDIP,

TSSOP

GND 11 — Ground

1IN– 2 I Inverting input, channel 1

2IN– 6 I Inverting input, channel 2

3IN– 9 I Inverting input, channel 3

4IN– 13 I Inverting input, channel 4

1IN+ 3 I Noninverting input, channel 1

2IN+ 5 I Noninverting input, channel 2

3IN+ 10 I Noninverting input, channel 3

4IN+ 12 I Noninverting input, channel 4

1OUT 1 O Output, channel 1

2OUT 7 O Output, channel 2

3OUT 8 O Output, channel 3

4OUT 14 O Output, channel 4

VCC 4 — Positive power supply

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to GND.

(3) Input voltage range is limited to 20 V or VCC + 5 V, whichever is smaller.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Voltage

Supply, VCC(2) 17

VDifferential input, VID –20 20

Input, VI(2)(3) 0 VCC + 5

Current Input, II–10 10 mA

Output, IO–10 10

Temperature

Operating, TAC-suffix versions 0 70

°C

I-suffix versions –40 125

Junction, TJ150

Storage, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

Machine model (MM) ±100

7.3 Recommended Operating Conditions

MIN MAX UNIT

Supply voltage, VCC

Single supply C-suffix versions 2.5 16

I-suffix versions 2.7 16

Split supply C-suffix versions ±1.25 ±8

I-suffix versions ±1.35 ±8

Common-mode input voltage, VICR –0.1 VCC + 5 V

Operating free-air

temperature, TA

C-suffix versions 0 70 °C

I-suffix versions –40 125

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(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal

Metrics

7.4 Thermal Information: TLV3401

THERMAL METRIC(1)

TLV3401

UNITD (SOIC) DBV (SOT-23) P (PDIP)

8 PINS 5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 201.9 237.8 58.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 92.5 108.7 48.3 °C/W

RθJB Junction-to-board thermal resistance 123.3 64.1 35.6 °C/W

ψJT Junction-to-top characterization parameter 23 12.1 25.9 °C/W

ψJB Junction-to-board characterization parameter 212.6 63.3 35.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal

Metrics

7.5 Thermal Information: TLV3402

THERMAL METRIC(1)

TLV3402

UNITD (SOIC) DGK (VSSOP) P (PDIP)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 201.9 186.8 58.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 92.5 77.5 48.3 °C/W

RθJB Junction-to-board thermal resistance 123.3 107.8 35.6 °C/W

ψJT Junction-to-top characterization parameter 23 15.7 25.9 °C/W

ψJB Junction-to-board characterization parameter 212.6 106.2 35.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal

Metrics

7.6 Thermal Information: TLV3404

THERMAL METRIC(1)

TLV3404

UNITD (SOIC) N (PDIP) PW (TSSOP)

14 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 83.8 65.5 120.8 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 70.7 20.0 34.3 °C/W

RθJB Junction-to-board thermal resistance 59.5 25.9 62.8 °C/W

ψJT Junction-to-top characterization parameter 11.6 1.9 1 °C/W

ψJB Junction-to-board characterization parameter 37.7 25.3 56.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

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(1) Full range is 0°C to 70°C for the C-suffix and –40°C to 125°C for the I-suffix. If not specified, full range is –40°C to 125°C.

7.7 Electrical Characteristics

At specified free-air temperature and VCC = 2.7 V, 5 V, 15 V, unless otherwise noted.

PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT

DC PERFORMANCE

VIO Input offset voltage VIC = VCC/2, RS= 50 Ω, RP= 1 MΩTA= 25°C 250 3600 µV

Full range 4400

αVIO Offset voltage drift VIC = VCC/2, RS= 50 Ω, RP= 1 MΩTA= 25°C 3 µV/°C

CMRR Common-mode rejection ratio

VIC = 0 V to 2.7 V, RS= 50 ΩTA= 25°C 55 72

Full range 50

VIC = 0 V to 5 V, RS= 50 ΩTA= 25°C 60 76

Full range 55

VIC = 0 V to 15 V, RS= 50 ΩTA= 25°C 65 88

Full range 60

AVD Large-signal differential voltage

amplification RP= 1 MΩTA= 25°C 1000 V/mV

INPUT/OUTPUT CHARACTERISTICS

IIO Input offset current VIC = VCC/2, RS= 50 Ω, RP= 1 MΩTA= 25°C 20 100 pA

Full range 1000

IIB Input bias current VIC = VCC/2, RS= 50 Ω, RP= 1 MΩTA= 25°C 80 250 pA

Full range 1500

ri(d) Differential input resistance TA= 25°C 300 MΩ

IOZ High-impedance output leakage

current VIC = VCC/2, VO= VCC, VID = 1 V TA= 25°C 50 pA

VOL Low-level output voltage

VIC = VCC/2, IOL = 2 µA, VID = –1 V TA= 25°C 8

VIC = VCC/2, IOL = 50 µA, VID = –1 V TA= 25°C 80 200

Full range 300

POWER SUPPLY

ICC Supply current (per channel) RP= no pullup

Output state low TA= 25°C 470 550

Full range 750

Output state high TA= 25°C 560 640

Full range 950

PSRR Power-supply rejection ratio VIC = VCC/2, no

load

VCC = 2.7 V to

5 V

TA= 25°C 75 100

Full range 70

VCC = 5 V to 15 V TA= 25°C 85 105

Full range 80

7.8 Switching Characteristics

At TA= 25°C, recommended operating conditions, and VCC = 2.7 V, 5 V, 15 V, unless otherwise noted.

PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT

t(PLH) Propagation delay time,

low-to-high-level output f = 10 kHz, VSTEP = 1 V,

RP= 1 MΩ, CL= 10 pF

Overdrive = 2 mV TA= 25°C 175

µs

Overdrive = 10

mV TA= 25°C 80

Overdrive = 50

mV TA= 25°C 55

t(PHL) Propagation delay time,

high-to-low-level output f = 10 kHz, VSTEP = 1 V,

RP= 1 MΩ, CL= 10 pF

Overdrive = 2 mV TA= 25°C 300

µs

Overdrive = 10

mV TA= 25°C 60

Overdrive = 50

mV TA= 25°C 30

tFFall time RP= 1 MΩ, CL= 10 pF TA= 25°C 5 µs

l TEXAS INSTRUMENTS 1200 Temperamre cc) 2400 Temperamre cc) anieve‘ empm Cunem (mA) anieve‘ empm Cunem (mm

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

Low-Level Output Voltage (V)

0 0.1 0.3 0.4 0.5 0.6 0.7 0.80.2

Low-Level Output Current (mA)

T = 25 C

A°

T = 70 C

A°

T = 0 C

A°

T = 40 C

A- °

T = 125 C

A°

V = 2.7 V

V = 1 V

ID -

4.5

3.5

2.5

1.5

0.5

Low-Level Output Voltage (V)

0 0.4 0.8 1.2 1.6 2 2.4 2.8

Low-Level Output Current (mA)

T = 25 C

A°

T = 70 C

A°

T = 0 C

A°

T = 40 C

A- °

T = 125 C

A°

V = 5 V

V = 1 V

ID -

1200

1000

800

600

400

200

-200

-40 -25 -10 520 35 50 65 80 95 110 125

Temperature (°C)

Input Bias/Offset Current (pA)

IIO

IIB

V = 15 V

2400

2000

1600

1200

800

400

-200

-40 -25 -10 520 35 50 65 80 95 110 125

Temperature ( C)°

Open-Collector Leakage Current (pA)

V = 1 V

2200

1800

1400

1000

600

200

V = 2.7 V, 5 V

V = 15 V

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7.9 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION FIGURE NO.

Input bias/offset current vs Free-air temperature Figure 1

Open collector leakage current vs Free-air temperature Figure 2

VOL Low-level output voltage vs Low-level output current Figure 3,Figure 4,

Figure 5

IDD Supply current vs Supply voltage Figure 6

IDD Supply current vs Free-air temperature Figure 7

Low-to-high level output response for various

input overdrives Figure 8,Figure 9,

Figure 10

High-to-low level output response for various

input overdrives Figure 11,Figure 12,

Figure 13

Output fall time vs Supply voltage Figure 14

Figure 1. Input Bias/Offset Current vs

Free-Air Temperature Figure 2. Open-Collector Leakage Current vs

Free-Air Temperature

Figure 3. Low-Level Output Voltage vs

Low-Level Output Current Figure 4. Low-Level Output Voltage vs

Low-Level Output Current

l TEXAS INSTRUMENTS anieve‘ Ompm Currem (mA) 700 Supp‘y Vanage (w mu Temperature we} vmmae (V) u Vanage (V) u Vanage (V)

-50 0 50 100 150 200 250 300

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 15 V, C = 10 pF

R = 1 M (pull up to V )

CC L

P CC

T = 25 C

A°

Output Voltage (V)

-50 0 50 100 150 200 250 300

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 5 V

C = 10 pF

R = 1 M (pull up to V )

P CC

T = 25 C

A°

700

600

500

400

300

200

100

-40 -25 -10 520 35 50 65 80 95 110 125

Temperature ( C)°

Supply Current (nA)

V = 2.7 V, 5 V, 15 V

V = 1 V

ID -

-50 0 50 100 150 200 250 300

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 2.7 V, C = 10 pF

R = 1 M (pull up to V )

CC L

P CC

T = 25 C

A°

2.5

1.5

0.5

Output Voltage (V)

700

600

500

400

300

200

100

0 2 46 8 10 12 14 16

Supply Voltage (V)

Supply Current (nA)

T = 125 C

A°

V = 1 V

ID -

T = 25 C

A°

T = 0 C

A°

T = 40 C

A- °

T = 70 C

A°

13.5

10.5

7.5

4.5

1.5

Low-Level Output Voltage (V)

0 1 3 456792 8

Low-Level Output Current (mA)

T = 25 C

A°

T = 70 C

A°

T = 0 C

A°

T = 40 C

A- °

T = 125 C

A°

V = 15 V

V = 1 V

ID -

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Figure 5. Low-Level Output Voltage vs

Low-Level Output Current Figure 6. Supply Current vs Supply Voltage

Figure 7. Supply Current vs Free-Air Temperature Figure 8. Low-to-High Level Output Response

for Various Input Overdrives

Figure 9. Low-to-High Level Output Response

for Various Input Overdrives Figure 10. Low-to-High Level Output Response

for Various Input Overdrives

l TEXAS INSTRUMENTS Vauage (v1 Supp‘y Vnhage M

Output Voltage (V)

-50 0 50 100 150 200 250 300 350 400

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 15 V, C = 10 pF

R = 1 M (pull up to V ),

CC L

P CC

WT = 25 C

A°

2 3 45678 9 10 11 12 13 14 15

Supply Voltage (V)

Output Fall Time ( s)m

V = 1 V to 1 V, T = 25 C

R = 1 m (pull up to V )

Input Fall Time = 500 ns

ID A

P CC

C = 50 pF

C = 10 pF

2.5

1.5

0.5

Output Voltage (V)

-50 0 50 100 150 200 250 300 350 400

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 2.7 V, C = 10 pF

R = 1 M (pull up to V )

CC L

P CC

T = 25 C

A°

-1

Output Voltage (V)

-50 0 50 100 150 200 250 300 350 400

Time ( s)m

0.05

0.1

Differential Input

Voltage (V)

2 mV

10 mV

50 mV

V = 5 V

C = 10 pF

R = 1 M (pull up to V )

P CC

T = 25 C

A°

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Figure 11. High-to-Low Level Output Response

for Various Input Overdrives Figure 12. High-to-Low Level Output Response

for Various Input Overdrives

Figure 13. High-to-Low Level Output Response

for Various Input Overdrives Figure 14. Output Fall Time vs Supply Voltage

l TEXAS INSTRUMENTS

IN+

IN±

VCC

GND

OUT

Input voltage

REF3312

1.25 V threshold voltage

Output voltage

RPULL-UP

Pull-up voltage

IN+

IN±

VCC

GND

OUT

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8 Detailed Description

8.1 Overview

The TLV340x is a family of nanopower comparators drawing only 470 nA per channel supply current. Having a

minimum operating supply voltage of 2.7 V over the extended industrial temperature range (TA= –40°C to

+125°C), while having an input common-mode range of –0.1 to VCC + 5 V makes this device ideal for battery-

powered and wireless handset applications.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Operating Voltage

The TLV340x comparators are specified for use on a single supply from 2.5 V to 16 V (or a dual supply from

±1.25 V to ±16 V) over a temperature range of −40°C to +125°C.

8.3.2 Setting the Threshold

Using a low-power, stable reference is important when setting the transition point for the TLV340x devices. The

REF3312, as shown in Figure 15, provides a 1.25-V reference voltage with low drift and only 3.9 µA of quiescent

current.

Figure 15. Setting the Threshold

8.4 Device Functional Modes

The TLV340x has a single functional mode and is operational when the power supply voltage applied ranges

from 2.5 V (±1.25 V) to 16 V (±8 V).

l TEXAS INSTRUMENTS

IN+

IN±

VCC

GND

OUT

Input voltage

REF3312

5 V

1.25 V threshold voltage

Output voltage

1 M

RPULL-UP

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Many applications require the detection of a signal (voltage or current) that exceeds a particular threshold voltage

or current. Using a comparator to make that threshold detection is the easiest, lowest power and highest speed

way to make a threshold detection.

9.2 Typical Application

Figure 16. 1.25-V Threshold Detector

9.2.1 Design Requirements

• Detect when a signal is above or below 1.25 V

• Operate from a single 5-V power supply

• Rail-to-rail input voltage range from 0 to 5 V

• Rail-to-rail output voltage range from 0 to 5 V

9.2.2 Detailed Design Procedure

The input voltage range in the circuit illustrated in Figure 16 is limited only by the power supply applied to the

TV3401. In this example with the selection of a 5-V, single-supply power supply, the input voltage range is limited

to 0 to VS+ 5 V, or 0 to 10 V. The threshold voltage of 1.25 V can de derived in a variety of ways. As the

TLV3401 is a very low-power device, it is desirable to also use very low power to create the threshold voltage.

The REF3312 series voltage reference is selected for its stable output voltage of 1.25 V and its low power

consumption of only 3.9 µA. The TLV3401 is an open-drain output comparator, requiring a pullup resistor from

output to the power supply. Proper selection of the pullup resistor value requires maximizing the output voltage

swing while at the same time minimizing power dissipated in the resistor when the output voltage is low. Too

small of a pullup resistor can result in too much power dissipation, while too large of a pullup resistor can result

in slower response times. The TLV3401 is fully specified with a 1-MΩpullup resistor and using a 1-MΩpullup

resistor results in meeting the performance specifications listed in the Electrical Characteristics.

l TEXAS INSTRUMENTS

Voltage at IN pin (V)

Output Voltage (V)

0 1 2 3 4 5

TLV3401

TLV3402

TLV3404

SLCS135B –AUGUST 2000–REVISED JANUARY 2017

www.ti.com

Product Folder Links: TLV3401 TLV3402 TLV3404

Typical Application (continued)

9.2.3 Application Curve

Figure 17. Transfer Function for the Threshold Detector

+IN

± IN

V+

OUT

10 F0.01 µF

3 4

Not to scale

Power supply

10 F0.01 µF

OUT

+IN ±IN

Power supply

RPULL-UP

TLV3401

TLV3402

TLV3404

www.ti.com

SLCS135B –AUGUST 2000–REVISED JANUARY 2017

Product Folder Links: TLV3401 TLV3402 TLV3404

10 Power Supply Recommendations

The TLV340x device is specified for operation from 2.5 V to 16 V (±1.25 to ±8 V); many specifications apply from

–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in Typical Characteristics.

11 Layout

11.1 Layout Guidelines

Figure 18 shows the typical connections for the TLV340x. To minimize supply noise, power supplies must be

capacitively decoupled by a 0.01-µF ceramic capacitor in parallel with a 10-µF electrolytic capacitor.

Comparators are very sensitive to input noise. Proper grounding (the use of a ground plane) helps to maintain

the specified performance of the TLV340x family.

For best results, maintain the following layout guidelines:

1. Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane.

2. Place a decoupling capacitor (0.1-µF ceramic, surface-mount capacitor) as close as possible to VCC.

3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback

around the comparator. Keep inputs away from the output.

4. Solder the device directly to the PCB rather than using a socket.

5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)

placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some

degradation to propagation delay when the impedance is low. The top-side ground plane runs between the

output and inputs.

6. The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the

outputs.

11.2 Layout Example

Figure 18. TLV340x Layout Example

l TEXAS INSTRUMENTS

TLV3401

TLV3402

TLV3404

SLCS135B –AUGUST 2000–REVISED JANUARY 2017

www.ti.com

Product Folder Links: TLV3401 TLV3402 TLV3404

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 DIP Adapter EVM

The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation

tool these TI packages: D or U (8-pin SOIC), PW (8-pin TSSOP), DGK (8-pin MSOP), DBV (6-pin SOT-23, 5-pin

SOT23, and 3-pin SOT-23), DCK (6-pin SC-70 and 5-pin SC-70), and DRL (6-pin SOT-563). The DIP Adapter

EVM may also be used with terminal strips or may be wired directly to existing circuits.

12.1.1.2 Universal Op Amp EVM

The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits

for a variety of IC package types. The evaluation module board design allows many different circuits to be

constructed easily and quickly. Five models are offered, with each model intended for a specific package type.

PDIP, SOIC, MSOP, TSSOP, and SOT-23 packages are all supported.

NOTE

These boards are unpopulated, so users must provide their own ICs. TI recommends

requesting several op amp device samples when ordering the Universal Op Amp EVM.

12.2 Documentation Support

12.2.1 Related Documentation

The following documents are relevant for using the TLV340x devices and are recommended for reference. All are

available for download at www.ti.com (unless otherwise noted):

•Universal Op Amp EVM User Guide (SLOU060)

•Hardware Pace using Slope Detection (SLAU511)

•Bipolar High-voltage Differential Interface for Low-voltage Comparators (TIDU039)

•AC-Coupled Single Supply Comparator (SLAU505)

•ECG Implementation on the TMS320VC5505 DSP Medical Development Kit (SPRAB36)

•REF33xx 3.9-μA, SC70-3, SOT-23-3, and UQFN-8, 30-ppm/ °C Drift Voltage Reference (SBOS392)

12.3 Related Links

Table 2 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

TLV3401 Click here Click here Click here Click here Click here

TLV3402 Click here Click here Click here Click here Click here

TLV3404 Click here Click here Click here Click here Click here

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

l TEXAS INSTRUMENTS

TLV3401

TLV3402

TLV3404

www.ti.com

SLCS135B –AUGUST 2000–REVISED JANUARY 2017

Product Folder Links: TLV3401 TLV3402 TLV3404

12.5 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.6 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.7 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TLV3401CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3401C

TLV3401CDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VBDC

TLV3401CDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VBDC

TLV3401ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3401I

TLV3401IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VBDI

TLV3401IDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VBDI

TLV3401IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VBDI

TLV3401IDBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VBDI

TLV3401IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3401I

TLV3401IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 TLV3401I

TLV3402CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3402C

TLV3402CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3402C

TLV3402CDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AJJ

TLV3402CDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AJJ

TLV3402CDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AJJ

TLV3402CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3402C

TLV3402CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3402C

TLV3402ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3402I

TLV3402IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3402I

TLV3402IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AJK

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TLV3402IDGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AJK

TLV3402IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AJK

TLV3402IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3402I

TLV3402IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3402I

TLV3402IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 TLV3402I

TLV3404CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3404C

TLV3404CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3404C

TLV3404CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3404C

TLV3404CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3404C

TLV3404ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

TLV3404IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

TLV3404IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

TLV3404IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 TLV3404I

TLV3404IPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

TLV3404IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

TLV3404IPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 3404I

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 3

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLV3401CDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TLV3401CDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TLV3401IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TLV3401IDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TLV3401IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV3402CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV3402CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV3402IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV3402IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV3404CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TLV3404CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TLV3404IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TLV3404IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV3401CDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0

TLV3401CDBVT SOT-23 DBV 5 250 210.0 185.0 35.0

TLV3401IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0

TLV3401IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0

TLV3401IDR SOIC D 8 2500 340.5 336.1 25.0

TLV3402CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0

TLV3402CDR SOIC D 8 2500 340.5 336.1 25.0

TLV3402IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0

TLV3402IDR SOIC D 8 2500 340.5 336.1 25.0

TLV3404CDR SOIC D 14 2500 340.5 336.1 32.0

TLV3404CPWR TSSOP PW 14 2000 853.0 449.0 35.0

TLV3404IDR SOIC D 14 2500 340.5 336.1 32.0

TLV3404IPWR TSSOP PW 14 2000 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

TLV3401CD D SOIC 8 75 507 8 3940 4.32

TLV3401ID D SOIC 8 75 507 8 3940 4.32

TLV3401IP P PDIP 8 50 506 13.97 11230 4.32

TLV3402CD D SOIC 8 75 507 8 3940 4.32

TLV3402CDG4 D SOIC 8 75 507 8 3940 4.32

TLV3402CDGK DGK VSSOP 8 80 330 6.55 500 2.88

TLV3402ID D SOIC 8 75 507 8 3940 4.32

TLV3402IDG4 D SOIC 8 75 507 8 3940 4.32

TLV3402IDGK DGK VSSOP 8 80 330 6.55 500 2.88

TLV3402IDGKG4 DGK VSSOP 8 80 330 6.55 500 2.88

TLV3402IP P PDIP 8 50 506 13.97 11230 4.32

TLV3404CD D SOIC 14 50 507 8 3940 4.32

TLV3404CPW PW TSSOP 14 90 530 10.2 3600 3.5

TLV3404ID D SOIC 14 50 507 8 3940 4.32

TLV3404IDG4 D SOIC 14 50 507 8 3940 4.32

TLV3404IN N PDIP 14 25 506 13.97 11230 4.32

TLV3404IPW PW TSSOP 14 90 530 10.2 3600 3.5

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/F 06/2021

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam AB, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddiﬁ§n%="" 5.40="" 5,40="" @eeeeeej="" rﬁhﬂ§eﬂhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com

MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end ﬂair \Meﬁead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com

PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Deﬁned Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA P (RiPMPi’E) "LAST‘C >4 >4 7 A V A A M Hnear dw‘ensmns are m inches (miH'nem's) B TH: druwmq is s bje“ :0 change thruut nonce C mus wmhm Juli"; Msiom vanmm BA NUTS DKMLiwi, N¥ PAL’KAC: 4 r ( “ V ‘ 7 v m 31H A H ‘ ‘ M H ‘—’ H w: H J; W“ D u‘ L , ,_ , 40mm: 04/2010 INSI'RUMENTS www.mzam

MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘ﬁ: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): noﬁce /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmﬂder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkﬂh INSI'RUMENTS www.1i.com

MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud ﬂasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com

LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Deﬁned Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH oﬂer eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com

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TLV3401,02,04 Datasheet by Texas Instruments

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