SN74HC165-EP Datasheet by Texas Instruments

T Component dualrtrcatron in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes but is not iirnited td Highly Accelerated Stress Test (HAST) or biased 55/35, temperature cycle, autoclave or unbiased HAST, eiectrornrgratron, bdnd intermetailic iile. and mold compound IiIe. Such qualilicalion testing snould not be viewed as justilying use at this component beyond speciried perIDrmance and environmental iii’niIS. descriptlon/ordering inlormation l—Il—Il—H—Il—Il—Ir—Il—I |_l|_l|_l|_l|_l|_lt_l|_l The SN74HC165 is an 87bit paralleHoad shift register that, when clocked, shifts the dat output. Parallei7in access to each stage is provided by eight individual direct data (A7H) i by a low level at the shift/load (SH/E) input. The SN74H0165 device also features a c lunctioh and a complementary serial (OH) output. Clocking is accomplished by a iowrto7high transition of the clock (CLK) input while SH/m INH is held low. The lunctiohs ol CLK and CLK INH are interchangeable. Since a low C transition of CLK INH also accomplish clocking, CLK INH should be changed to the hig is high. Parallel loading is inhibited when SH/m is held high. While SH/m is low, the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) i ORDERING INFORMATION ORDERABLE TOP-SI TA PACKAGE: PART NUMBER MARKI SOiC 7 D Tape and reel SN74HCIBSQDREP HCTGSEP 740°C to 125°C TSSOF 7 PW Tape and reel SN74HCIBSQFWREF HCTGSEP 755°Cl0125§0 SOiC 7 D Tape and reel SN74HCIBSMDREP HCTGSMEF i Package drawings available at www.ii com/sc/package standard packing quantities, thermal data, symoorrzatron. and PCB design guide Please be aware that an important notice concerning availability, standard warranty, and use Texas instruments semiconductor products and disclaimers theretc appears at tne end or this data sh ‘4‘ TEXAS INSTRUMENTS POST omcg cox 555303 - DALLAS. TEXAS 75285
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of Up
To −55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
D2-V to 6-V VCC Operation
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 13 ns
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DComplementary Outputs
DDirect Overriding Load (Data) Inputs
DGated Clock Inputs
DParallel-to-Serial Data Conversion
description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (QH)
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH)
function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION
TAPACKAGE‡ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 125°C
SOIC − D Tape and reel SN74HC165QDREP HC165EP
−40°C to 125°CTSSOP − PW Tape and reel SN74HC165QPWREP HC165EP
−55°C to 125°CSOIC − D Tape and reel SN74HC165MDREP HC165MEP
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
QH
GND
VCC
CLK INH
D
C
B
A
SER
QH
Copyright 2004, Texas Instruments Incorporated
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"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
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H L T 5mm H T L 5mm T Sm“ : cement a! each mlema‘ regxster shms toward sena‘ outpm 0H, Data at SER \s shmed mto me first regwster logic diagram (positive logic) A a SH/fi 1 c{> ‘ “by b b b a d b CLK s s s s s s s s 10 CI 7 c1 7 CI 7 c1 7 «:1 CI 7 CI 7 CI SER4> ID 1D ID 1D ID ID 1D ID R R ‘9 TEXAS INSTRUMENTS 9057 omca aox 555303 - DALLAS IEXAS 752s5
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD CLK CLK INH FUNCTION
L X X Parallel load
HH X No change
HX H No change
H L ↑Shift†
H↑L Shift†
†Shift = content of each internal register shifts
toward serial output QH. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1 S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
QH
11 12 13 14 3 4 5 6
ABCDEFGH
INSTRUMENTS ‘4; TEXAS
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical shift, load, and inhibit sequence
Load
E
QH
H
G
C
F
Data
Inputs D
SH/LD
SER
CLK INH
CLK
B
A
QH
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
Inhibit Serial Shift
ngMeve‘ mpm vanage Loleevel mpm voltage Input transmon nsenan ume ‘9 TEXAS INSTRUMENTS
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2):D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2
V
VCC = 2 V 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8
V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
VCC = 2 V 1000
∆t/∆v‡Input transition rise/fall time VCC = 4.5 V 500 ns
∆t/∆v‡
Input transition rise/fall time
VCC = 6 V 400
ns
TA
Operating free-air temperature
Q-suffix device −40 125
°C
T
A
Operating free-air temperature
M-suffix device −55 125 °
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
{OH : 720 “A Vl : VIH oerL Vl : VIH oerL v‘ : v00 v‘ : v00 ‘4‘ TEXAS INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
V
CC MIN TYP MAX
MIN
MAX
UNIT
2 V 1.9 1.998 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.999 5.9 V
VOH
VI = VIH or VIL
IOH = −4 mA 4.5 V 3.98 4.3 3.7
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2
2 V 0.002 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.001 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 8 160 µA
Ci2 V to 6 V 3 10 10 pF
'clack Cluck frequency SHE law CLK mgn or mw SHE mgn nemre CLKT SER befiore CLKT lsu Setup ume CLK JNH law belare CLKT CLK JNH hwgh bemre CLKT Data nature swfii SER data afler CLKT PAR data alter swfii ‘9 TEXAS INSTRUMENTS
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
MIN
MAX
UNIT
V
CC MIN MAX
MIN
MAX
UNIT
2 V 6 4.2
f
clock
Clock frequency 4.5 V 31 21 MHz
fclock
Clock frequency
6 V 36 25
MHz
2 V 80 120
SH/LD low 4.5 V 16 24
tw
Pulse duration
SH/LD low
6 V 14 20
ns
twPulse duration 2 V 80 120 ns
CLK high or low 4.5 V 16 24
CLK high or low
6 V 14 20
2 V 80 120
SH/LD high before CLK↑4.5 V 16 24
SH/LD high before CLK↑
6 V 14 20
2 V 40 60
SER before CLK↑4.5 V 8 12
SER before CLK↑
6 V 7 10
2 V 100 150
t
su
Setup time CLK INH low before CLK↑4.5 V 20 30 ns
tsu
Setup time
CLK INH low before CLK↑
6 V 17 25
ns
2 V 40 60
CLK INH high before CLK↑4.5 V 8 12
CLK INH high before CLK↑
6 V 7 10
2 V 100 150
Data before SH/LD↓4.5 V 20 30
Data before SH/LD↓
6 V 17 26
2 V 5 5
SER data after CLK↑4.5 V 5 5
th
Hold time
SER data after CLK↑
6 V 5 5
ns
t
h
Hold time
2 V 5 5
ns
PAR data after SH/LD↓4.5 V 5 5
PAR data after SH/LD↓
6 V 5 5
'max ‘4‘ TEXAS INSTRUMENTS
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX
MIN
MAX
UNIT
2 V 6 13 4.2
f
max
4.5 V 31 50 21 MHz
fmax
6 V 36 62 25
MHz
2 V 80 150 225
SH/LD Q
H
or Q
H
4.5 V 20 30 45
SH/LD
QH or QH
6 V 16 26 38
2 V 75 150 225
t
pd
CLK Q
H
or Q
H
4.5 V 15 30 45 ns
tpd
CLK
QH or QH
6 V 13 26 38
ns
2 V 75 150 225
H Q
H
or Q
H
4.5 V 15 30 45
H
QH or QH
6 V 13 26 38
2 V 38 75 110
t
t
Any 4.5 V 8 15 22 ns
tt
Any
6 V 6 13 19
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 75 pF
11 % “w» \LV 1# 1L ‘ k a 4% “a \\+\\\ Lw W ‘m p 4 J w L INSTRUMENTS ‘4" TEXAS
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10%
90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50%
V
CC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10%
90% 90%
VC
C
VO
H
VO
L
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10%
90%90% VO
H
VO
L
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC165QPWREP ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC165EP
V62/04689-01YE ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC165EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
OTHER QUALIFIED VERSIONS OF SN74HC165-EP :
•Catalog: SN74HC165
•Automotive: SN74HC165-Q1
•Military: SN54HC165
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC165QPWREP TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC165QPWREP TSSOP PW 16 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
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EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
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EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
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