ADC12DS105 Datasheet by Texas Instruments

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ADC12DS105 Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs

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1FEATURES DESCRIPTION

The ADC12DS105 is a high-performance CMOS

2• Clock Duty Cycle Stabilizer analog-to-digital converter capable of converting two

• Single +3.0 or 3.3V Supply Operation analog input signals into 12-bit digital words at rates

• Serial LVDS Outputs up to 105 Mega Samples Per Second (MSPS). The

digital outputs are serialized and provided on

• Serial Control Interface differential LVDS signal pairs. This converter uses a

• Overrange Outputs differential, pipelined architecture with digital error

• 60-pin WQFN Package, (9x9x0.8mm, 0.5mm correction and an on-chip sample-and-hold circuit to

pin-pitch) minimize power consumption and the external

component count, while providing excellent dynamic

performance. The ADC12DS105 may be operated

APPLICATIONS from a single +3.0V or 3.3V power supply. A power-

• High IF Sampling Receivers down feature reduces the power consumption to very

• Wireless Base Station Receivers low levels while still allowing fast wake-up time to full

operation. The differential inputs accept a 2V full

• Test and Measurement Equipment scale differential input swing. A stable 1.2V internal

• Communications Instrumentation voltage reference is provided, or the ADC12DS105

• Portable Instrumentation can be operated with an external 1.2V reference. The

selectable duty cycle stabilizer maintains

KEY SPECIFICATIONS performance over a wide range of clock duty cycles.

A serial interface allows access to the internal

• Resolution: 12 Bits registers for full control of the ADC12DS105's

• Conversion Rate: 105 MSPS functionality. The ADC12DS105 is available in a 60-

lead WQFN package and operates over the industrial

• SNR (fIN = 240 MHz): 68.5 dBFS (typ) temperature range of −40°C to +85°C

• SFDR (fIN = 240 MHz): 83 dBFS (typ)

• Full Power Bandwidth: 1 GHz (typ)

• Power Consumption: 1 W (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

{yﬁmﬁ INSTRUMENTS UUUUUUUUUUUUUUU 22222222222222: HHHHHHHHHHHHHHH 222222222222222 L: : v v

12-Bit Pipelined

ADC Core

Parallel

-to-

Serial

Reference

DLL

Timing

Generation

SPI

Interface

Control

Registers

VINA2 12

SD0_A

SD1_A

CHANNEL A

12-Bit Pipelined

ADC Core

Parallel

-to-

Serial

VINB2 12

SD0_B

SD1_B

CHANNEL B

FRAME

OUTCLK

CLK

VREF

Ref.Outputs

ORB

ORA

SCSb

SCLK

SPI_EN

SDI

SDO

ADC12DS105

(top view)

OF/DCS

CLK

VDR

N/C

DRGND

PD_A

WAM

VRPA

PD_B

TEST

VDR

VREF

SCSb

SPI_EN

DLC

DRGND

OUTCLK+

N/C

SD0_B-

OUTCLK-

FRAME-

FRAME+

VINA-

VINA+

AGND

VINB-

ORA

VCMOA

VRNA

VCMOB

VRNB

VRPB

N/C

DLL_Lock

Reset_DLL

LVDS_Bias

ORB

SD0_B+

SD1_B-

SD1_B+

DRGND

SD0_A-

SD0_A+

SD1_A-

SD1_A+

SDI

SDO

SCLK

* Exposed Pad

VINB+

N/C

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Connection Diagram

Figure 1. WQFN Package

See Package Number NKA0060A

Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

3 VINA+

13 VINB+

Differential analog input pins. The differential full-scale input signal

level is 2VP-P with each input pin signal centered on a common mode

2 VINA- voltage, VCM.

14 VINB-

5 VRPA

11 VRPB

7 VCMOA

9 VCMOB

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close to

the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor

should be placed between VRP and VRN as close to the pins as

possible, and a 1 µF capacitor should be placed in parallel.

VRP and VRN should not be loaded. VCMO may be loaded to 1mA for

6 VRNAuse as a temperature stable 1.5V reference.

10 VRNBIt is recommended to use VCMO to provide the common mode

voltage, VCM, for the differential analog inputs.

Reference Voltage. This device provides an internally developed

1.2V reference. When using the internal reference, VREF should be

decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series

59 VREF inductance (ESL) capacitor.

This pin may be driven with an external 1.2V reference voltage.

This pin should not be used to source or sink current.

LVDS Driver Bias Resistor is applied from this pin to Analog Ground.

29 LVDS_Bias The nominal value is 3.6KΩ

DIGITAL I/O

The clock input pin.

18 CLK The analog inputs are sampled on the rising edge of the clock input.

Reset_DLL input. This pin is normally low. If the input clock

frequency is changed abruptly, the internal timing circuits may

28 Reset_DLL become unlocked. Cycle this pin high for 1 microsecond to re-lock

the DLL. The DLL will lock in several microseconds after Reset_DLL

is asserted.

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Pin Descriptions and Equivalent Circuits (continued)

Pin No. Symbol Equivalent Circuit Description

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = VA, output data format is 2's complement without duty

cycle stabilization applied to the input clock

OF/DCS = AGND, output data format is offset binary, without duty

cycle stabilization applied to the input clock.

19 OF/DCS OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle

stabilization applied to the input clock

OF/DCS = (1/3)*VA, output data is offset binary with duty cycle

stabilization applied to the input clock.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

This is a two-state input controlling Power Down.

PD = VA, Power Down is enabled and power dissipation is reduced.

57 PD_A PD = AGND, Normal operation.

20 PD_B Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Test Mode. When this signal is asserted high, a fixed test pattern

(101001100011 msb->lsb) is sourced at the data outputs.

With this signal deasserted low, the device is in normal operation

27 TEST mode.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Word Alignment Mode.

In single-lane mode this pin must be set to logic-0.

In dual-lane mode only, when this signal is at logic-0 the serial data

47 WAM words are offset by half-word. With this signal at logic-1 the serial

data words are aligned with each other.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Dual-Lane Configuration. The dual-lane mode is selected when this

signal is at logic-0. With this signal at logic-1, all data is sourced on a

48 DLC single lane (SD1_x) for each channel.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

Serial Clock. This pair of differential LVDS signals provides the serial

clock that is synchronous with the Serial Data outputs. A bit of serial

data is provided on each of the active serial data outputs with each

45 OUTCLK+ falling and rising edge of this clock. This differential output is always

44 OUTCLK- enabled while the device is powered up. In power-down mode this

output is held in logic-low state. A 100-ohm termination resistor must

always be used between this pair of signals at the far end of the

transmission line.

Serial Data Frame. This pair of differential LVDS signals transitions

at the serial data word boundaries. The SD1_A+/- and SD1_B+/-

output words always begin with the rising edge of the Frame signal.

The falling edge of the Frame signal defines the start of the serial

43 FRAME+ data word presented on the SD0_A+/- and SD0_B+/- signal pairs in

42 FRAME- the Dual-Lane mode. This differential output is always enabled while

the device is powered up. In power-down mode this output is held in

logic-low state. A 100-ohm termination resistor must always be used

between this pair of signals at the far end of the transmission line.

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VDR

DGND

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Pin Descriptions and Equivalent Circuits (continued)

Pin No. Symbol Equivalent Circuit Description

Serial Data Output 1 for Channel A. This is a differential LVDS pair

of signals that carries channel A ADC’s output in serialized form. The

serial data is provided synchronous with the OUTCLK output. In

Single-Lane mode each sample’s output is provided in succession.

38 SD1_A+ In Dual-Lane mode every other sample output is provided on this

37 SD1_A- output. This differential output is always enabled while the device is

powered up. In power-down mode this output holds the last logic

state. A 100-ohm termination resistor must always be used between

this pair of signals at the far end of the transmission line.

Serial Data Output 1 for Channel B. This is a differential LVDS pair

of signals that carries channel B ADC’s output in serialized form. The

serial data is provided synchronous with the OUTCLK output. In

Single-Lane mode each sample’s output is provided in succession.

34 SD1_B+ In Dual-Lane mode every other sample output is provided on this

33 SD1_B- output. This differential output is always enabled while the device is

powered up. In power-down mode this output holds the last logic

state. A 100-ohm termination resistor must always be used between

this pair of signals at the far end of the transmission line.

Serial Data Output 0 for Channel A. This is a differential LVDS pair

of signals that carries channel A ADC’s alternating samples’ output

in serialized form in Dual-Lane mode. The serial data is provided

synchronous with the OUTCLK output. In Single-Lane mode this

36 SD0_A+ differential output is held in high impedance state. This differential

35 SD0_A- output is always enabled while the device is powered up. In power-

down mode this output holds the last logic state. A 100-ohm

termination resistor must always be used between this pair of signals

at the far end of the transmission line.

Serial Data Output 0 for Channel B. This is a differential LVDS pair

of signals that carries channel B ADC’s alternating samples’ output

in serialized form in Dual-Lane mode. The serial data is provided

synchronous with the OUTCLK output. In Single-Lane mode this

32 SD0_B+ differential output is held in high impedance state. This differential

31 SD0_B- output is always enabled while the device is powered up. In power-

down mode this output holds the last logic state. A 100-ohm

termination resistor must always be used between this pair of signals

at the far end of the transmission line.

SPI Enable: The SPI interface is enabled when this signal is

asserted high. In this case the direct control pins have no effect.

56 SPI_EN When this signal is deasserted, the SPI interface is disabled and the

direct control pins are enabled.

Serial Chip Select: While this signal is asserted SCLK is used to

accept serial data present on the SDI input and to source serial data

55 SCSb on the SDO output. When this signal is deasserted, the SDI input is

ignored and the SDO output is in tri-state mode.

Serial Clock: Serial data are shifted into and out of the device

52 SCLK synchronous with this clock signal.

Serial Data-In: Serial data are shifted into the device on this pin

while SCSb signal is asserted.

54 SDI

Serial Data-Out: Serial data are shifted out of the device on this pin

53 SDO while SCSb signal is asserted. This output is in tri-state mode when

SCSb is deasserted.

Overrange. These CMOS outputs are asserted logic-high when their

46 ORA respective channel’s data output is out-of-range in either high or low

30 ORB direction.

DLL_Lock Output. When the internal DLL is locked to the input CLK,

this pin outputs a logic high. If the input CLK is changed abruptly, the

24 DLL_Lock internal DLL may become unlocked and this pin will output a logic

low. Cycle Reset_DLL (pin 28) to re-lock the DLL to the input CLK.

ANALOG POWER

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Pin Descriptions and Equivalent Circuits (continued)

Pin No. Symbol Equivalent Circuit Description

Positive analog supply pins. These pins should be connected to a

8, 16, 17, 58, VAquiet source and be bypassed to AGND with 0.1 µF capacitors

60 located close to the power pins.

1, 4, 12, 15, AGND The ground return for the analog supply.

Exposed Pad

DIGITAL POWER

Positive driver supply pin for the output drivers. This pin should be

26, 40, 50 VDR connected to a quiet voltage source and be bypassed to DRGND

with a 0.1 µF capacitor located close to the power pin.

The ground return for the digital output driver supply. This pins

25, 39, 51 DRGND should be connected to the system digital ground, but not be

connected in close proximity to the ADC's AGND pins.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)(3)

Supply Voltage (VA, VDR)−0.3V to 4.2V

Voltage on Any Pin (Not to exceed 4.2V) −0.3V to (VA+0.3V)

Input Current at Any Pin other than Supply Pins(4) ±5 mA

Package Input Current(4) ±50 mA

Max Junction Temp (TJ) +150°C

Thermal Resistance (θJA) 30°C/W

ESD Rating Human Body Model(5) 2500V

Machine Model(5) 250V

Storage Temperature −65°C to +150°C

Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(6)

(1) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be

limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of ±5 mA to 10.

(5) Human Body Model is 100 pF discharged through a 1.5 kΩresistor. Machine Model is 220 pF discharged through 0 Ω

(6) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Operating Ratings(1)(2)

Operating Temperature −40°C ≤TA≤+85°C

Supply Voltage (VA=VDR) +2.7V to +3.6V

Clock Duty Cycle (DCS Enabled) 30/70 %

(DCS Disabled) 45/55 %

VCM 1.4V to 1.6V

|AGND-DRGND| ≤100mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤

TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits (min)

2LSB (max)

INL Integral Non Linearity ±0.5 -2 LSB (min)

0.8 LSB (max)

DNL Differential Non Linearity ±0.3 -0.8 LSB (min)

PGE Positive Gain Error 0.15 ±1 %FS (max)

NGE Negative Gain Error 0.07 ±1 %FS (max)

TC PGE Positive Gain Error Tempco −40°C ≤TA≤+85°C ppm/°C

TC NGE Negative Gain Error Tempco −40°C ≤TA≤+85°C ppm/°C

VOFF Offset Error 0.03 ±0.55 %FS (max)

TC VOFF Offset ErrorTempco −40°C ≤TA≤+85°C ppm/°C

Under Range Output Code 0 0

Over Range Output Code 4095 4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

1.4 V (min)

VCMO Common Mode Output Voltage 1.5 1.6 V (max)

1.4 V (min)

VCM Analog Input Common Mode Voltage 1.5 1.6 V (max)

(CLK LOW) 8.5 pF

VIN Input Capacitance (each pin to VIN = 1.5 Vdc ± 0.5

CIN GND)(4) V(CLK HIGH) 3.5 pF

1.17 V (min)

VREF Internal Reference Voltage 1.18 1.21 V (max)

TC VREF Internal Reference Voltage Tempco −40°C ≤TA≤+85°C 18 ppm/°C

VRP Internal Reference Top 2.0 V

VRN Internal Reference Bottom 1.0 V

0.89 V (min)

Internal Reference Accuracy (VRP-VRN) 0.97 1.06 V (max)

EXT 1.176 V (min)

External Reference Voltage 1.2

VREF 1.224 V (max)

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

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Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin, . Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA

≤TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)(4)

DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS

FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner 1.0 GHz

fIN = 10 MHz 71 dBFS

SNR Signal-to-Noise Ratio fIN = 70 MHz 70 dBFS

fIN = 240 MHz 68.5 67.4 dBFS

fIN = 10 MHz 88 dBFS

SFDR Spurious Free Dynamic Range fIN = 70 MHz 85 dBFS

fIN = 240 MHz 83 76.5 dBFS

fIN = 10 MHz 11.5 Bits

ENOB Effective Number of Bits fIN = 70 MHz 11.3 Bits

fIN = 240 MHz 11 10.7 Bits

fIN = 10 MHz −86 dBFS

THD Total Harmonic Disortion fIN = 70 MHz −85 dBFS

fIN = 240 MHz −80 -74 dBFS

fIN = 10 MHz −90 dBFS

H2 Second Harmonic Distortion fIN = 70 MHz −88 dBFS

fIN = 240 MHz −83 -76.5 dBFS

fIN = 10 MHz −88 dBFS

H3 Third Harmonic Distortion fIN = 70 MHz −85 dBFS

fIN = 240 MHz −83 -76.5 dBFS

fIN = 10 MHz 70.8 dBFS

SINAD Signal-to-Noise and Distortion Ratio fIN = 70 MHz 69.9 dBFS

fIN = 240 MHz 68.2 66.5 dBFS

fIN = 19.5 and 20.5 MHz,

IMD Intermodulation Distortion -82 dBFS

each -7dBFS

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4) This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal.

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Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Boldface limits apply for TMIN ≤TA≤

TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)

DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC)

VIN(1) Logical “1” Input Voltage VD= 3.6V 2.0 V (min)

VIN(0) Logical “0” Input Voltage VD= 3.0V 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA

IIN(0) Logical “0” Input Current VIN = 0V −10 µA

CIN Digital Input Capacitance 5 pF

DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO,DLL_Lock)

VOUT(1) Logical “1” Output Voltage IOUT =−0.5 mA 1.2 V (min)

VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA 0.4 V (max)

+ISC Output Short Circuit Source Current VOUT = 0V −10 mA

−ISC Output Short Circuit Sink Current VOUT = VDR 10 mA

COUT Digital Output Capacitance 5 pF

POWER SUPPLY CHARACTERISTICS

IAAnalog Supply Current Full Operation 240 270 mA (max)

IDR Digital Output Supply Current Full Operation 70 80 mA

Power Consumption 1000 1130 mW (max)

Power Down Power Consumption Clock disabled 33 mW

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Timing measurements are taken at

50% of the signal amplitude. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)

In Single-Lane Mode 65

Maximum Clock Frequency MHz (max)

In Dual-Lane Mode 105

In Single-Lane Mode 25

Minimum Clock Frequency MHz (min)

In Dual-Lane Mode 52.5

Single-Lane Mode 7.5

tCONV Conversion Latency Dual-Lane, Offset Mode 8Clock Cycles

Dual-Lane, Word Aligned Mode 9

tAD Aperture Delay 0.6 ns

tAJ Aperture Jitter 0.1 ps rms

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

Serial Control Interface Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= 3.3V, VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Timing measurements are taken at 50%

of the signal amplitude. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)

fSCLK Serial Clock Frequency fSCLK = fCLK/10 10.5 MHz (max)

40 % (min)

tPH SCLK Pulse Width - High % of SCLK Period 60 % (max)

40 % (min)

tPL SCLK Pulse Width - Low % of SCLK Period 60 % (max)

tSU SDI Setup Time 5 ps (min)

tHSDI Hold Time 5 ns (min)

tODZ SDO Driven-to-Tri-State Time 40 50 ns (max)

tOZD SDO Tri-State-to-Driven Time 15 20 ns (max)

tOD SDO Output Delay Time 15 20 ns (max)

tCSS SCSb Setup Time 5 10 ns (min)

tCSH SCSb Hold Time 5 10 ns (min)

Minimum time SCSb must be deasserted Cycles of

tIAG Inter-Access Gap 3

between accesses SCLK

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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LVDS Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Timing measurements are taken at

50% of the signal amplitude. Boldface limits apply for TMIN ≤TA≤TMAX.All other limits apply for TA= 25°C(1)(2)

Units

Parameter Test Conditions Typical(3) Limits (Limits)

LVDS DC CHARACTERISTICS

Output Differential Voltage 250 mV (min)

VOD RL= 100Ω350

(SDO+) - (SDO-) 450 mV (max)

delta Output Differential Voltage Unbalance RL= 100Ω±25 mV (max)

VOD

1.125 V (min)

VOS Offset Voltage RL= 100Ω1.25 1.375 V (max)

delta VOS Offset Voltage Unbalance RL= 100Ω±25 mV (max)

IOS Output Short Circuit Current DO = 0V, VIN = 1.1V, -10 mA (max)

LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS

tDP Output Data Bit Period Dual-Lane Mode 1.59 ns

Output Data Edge to Output Clock Edge

tHO Dual-Lane Mode 750 450 ps

Hold Time(4)

Output Data Edge to Output Clock Edge

tSUO Dual-Lane Mode 800 500 ps

Set-Up Time(4)

tFP Frame Period Dual-Lane Mode 19.05 ns

45 % (min)

tFDC Frame Clock Duty Cycle(4) 50 55 % (max)

tDFS Data Edge to Frame Edge Skew 50% to 50% 15 ps

From rising edge of CLK to ORA/ORB

tODOR Output Delay of OR output 4 ns

valid

(1) The inputs are protected as shown below. Input voltage magnitudes above VAor below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2) With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3) Typical figures are at TA= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4) This parameter is specified by design and/or characterization and is not tested in production.

Figure 2.

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VD+

VD-

VOS

GND VOD = | VD+ - VD- |

VOD

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Specification Definitions

APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (VCM)is the common DC voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

CROSSTALK is coupling of energy from one channel into the other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error −Negative Full Scale Error (1)

It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error (2)

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight

line. The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,

where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.

LVDS Differential Output Voltage (VOD)is the absolute value of the difference between the differential output

pair voltages (VD+ and VD-), each measured with respect to ground.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is specified not to

have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition

from code 2047 to 2048.

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OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply

limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

(3)

where f1is the RMS power of the fundamental (output) frequency and f2through f7are the RMS power of the first

six harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in

the input frequency at the output and the power in its 2nd harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in

the input frequency at the output and the power in its 3rd harmonic level at the output.

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OUTCLK

D11

D10

D11

tFP = tSAMPLE

VINA

VINB

CLK

Sample

N+1

Sample

N+2

tSD

tDP = tSAMPLE/12

FRAME

SD1_A,

SD1_B

Sample N-1 Sample N Sample N+1

tSAMPLE = 1/fCLK

Sample N Sample N+1

ORA,

ORB

D11

OUTCLK

Valid Data

tSUO

Valid Data

tHO

Valid Data

tDP tDP

SData

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Timing Diagrams

Figure 3. Serial Output Data Timing

Figure 4. Serial Output Data Format in Single-Lane Mode

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l TEXAS INSTRUMENTS OFFSET MODE wonurmeNau MODE 3

Sample N+1

Sample N

OUTCLK

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11D0

tFP = 2 x tSAMPLE

VINA

VINB

CLK

Sample

Sample N+1

Sample

N+2

tSD

tDP = tSAMPLE/6

FRAME

SD1_A,

SD1_B

tSAMPLE = 1/fCLK

D11 D10 D9 D8 D7 D6D0

SD0_A,

SD0_B D5 D4 D3 D2 D1

Sample N-1

Sample N-2

Sample N+1

ORA,

ORB

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D0

SD1_A,

SD1_B D1

SD0_A,

SD0_B

Sample N

Sample N-2

ORA,

ORB Sample N Sample N+1

tDP

OFFSET MODE :

WORD-ALIGNED MODE :

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D0D1

Sample N+1Sample N-1

Sample

N+2

Sample

N+3

Sample N

D10 D9

D5 D4 D3D7 D6

D11 D10 D9

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Figure 5. Serial Output Data Format in Dual-Lane Mode

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l TEXAS INSTRUMENTS DNL (LSB) 00mm Code \ VHH HMmQS) ,4“ POSWWE wn-scm , FquscALE pow / TRANSWDN , (v30) munmnunnaa (2m) ,, ,, ,, r waz mmscm , a F orrsn rwsmoN / man my, ’ (w) < (w)="" mn=""> 1w} ampmamm (2‘, awnnma‘onn‘ <4; auummmnuam="" |="" i="" 4="" vref="" um="" 44="" vm="" ana‘og="" mm="" voltage="" (vw)="" —(v,n—)="" 1="" o="" 1="" o="" o="" 5="" o="" 5="" '="" '="" .="" e="" to="" 4="" o="" 0="" j="" o="" 0="" z="" ,0="" 5="" ,0="" 5="" 4="" o="" 4="" o="" o="" 1024="" 2043="" 3072="" 4006="" o="" 1024="" 2043="" 3072="" 4006="" code="" code="">

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Transfer Characteristic

Figure 6. Transfer Characteristic

Typical Performance Characteristics DNL, INL

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, TA= 25°C.

DNL INL

Figure 7. Figure 8.

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l TEXAS INSTRUMENTS 100 -70 \ F =240 MH FIN=240MH1 'N z a :3 A 3 9° 3 THD g SFDR 1%, '50 —\ ~_’ ﬂ \/ S /_ 6 so : 3RD HARM § 5 \ \— 7; 5 .90 m» SNR E 2ND HARM 2 70 = ”’ SINAD 3 o 3 3 3.3 3.0 3 3 3.3 VA M VA (V) 100 -70 § FDR A 5 9° 5 a E \ g 430 g 2 6 so 2 THD / < c:="" e="" 0="" 2nd="" harm="" 1/)="" snr="" 5="" -9o="" \="" cc'="" e="" .="" 7::="" \j="">L SINAD m V 3RD HARM so 400 ‘ 4a 45 50 55 an 45 50 55 an CLOCK DUTY CYCLE (%) CLOCK nu‘rv CYCLE m) 100 -70 a :3 A 3 so g FDR 4m § 5 g u) o d 50 5 THE 2 o 2ND HARM (/2 SNR 5 .90 _, cé 70 E 3RD HARM % SINAD so 400 30 4o 50 so 70 3o 40 50 so 70 CLOCK DUTY CYCLE (%) CLOCK DUTV CYCLE (%)

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Typical Performance Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, TA= 25°C.

SNR, SINAD, SFDR vs. VADistortion vs. VA

Figure 9. Figure 10.

SNR, SINAD, SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle

Figure 11. Figure 12.

SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled Distortion vs. Clock Duty Cycle, DCS Enabled

Figure 13. Figure 14.

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l TEXAS INSTRUMENTS 0 0 720 720 .40 .40 m m u. u. g -60 g -60 -50 -50 4 oo ' ' I ' 4 oo 4 20 4 20 00 175 350 525 00 175 350 525 FREQUENCY (MHz) FREQUENCY (MHz) 0 0 720 720 .40 .40 m m u. u. g -60 g -60 -50 -50 4 oo 4 oo 4 20 4 20 00 175 350 525 00 175 350 525 FREQUENCY (MHI) FREQUENCY (MHI)

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Typical Performance Characteristics (continued)

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA= +3.3V, VDR = +3.0V, Internal VREF

= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, TA= 25°C.

Spectral Response @ 10 MHz Input Spectral Response @ 70 MHz Input

Figure 15. Figure 16.

Spectral Response @ 240 MHz Input IMD, fIN1 = 20 MHz, fIN2 = 21 MHz

Figure 17. Figure 18.

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FUNCTIONAL DESCRIPTION

Operating on a single +3.3V supply, the ADC12DS105 digitizes two differential analog input signals to 12 bits,

using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to

ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or using an

external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty cycle

stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 19). The output

data can be set for offset binary or two's complement.

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12DS105:

2.7V ≤VA≤3.6V

2.7V ≤VDR ≤VA

25 MHz ≤fCLK ≤105 MHz

1.2V internal reference

VREF = 1.2V (for an external reference)

VCM = 1.5V (from VCMO)

ANALOG INPUTS

Signal Inputs

Differential Analog Input Pins

The ADC12DS105 has a pair of analog signal input pins for each of two channels. VIN+ and VIN−form a

differential input pair. The input signal, VIN, is defined as

VIN = (VIN+) – (VIN−) (4)

Figure 19 shows the expected input signal range. Note that the common mode input voltage, VCM, should be

1.5V. Using VCMO (pins 7,9) for VCM will ensure the proper input common mode level for the analog input signal.

The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the

differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and

be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or

the output data will be clipped.

Figure 19. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB can be described as approximately

EFS = 4096 ( 1 - sin (90° + dev)) (5)

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ADC

Input

3 pF

VCMO

0.1 PF

VIN

ETC1-1-13

0.1 PF

100:

ETC1-1-13

ADC

Input

18 pF

VCMO

0.1 PF

VIN ADT1-1WT

50:0.1 PF

20:

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Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship

to each other (see Figure 20). For single frequency inputs, angular errors result in a reduction of the effective full

scale input. For complex waveforms, however, angular errors will result in distortion.

Figure 20. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source

impedance for the differential inputs will improve even ordered harmonic performance (particularly second

harmonic).

Table 1 indicates the input to output relationship of the ADC12DS105.

Table 1. Input to Output Relationship

VIN+VIN−Binary Output 2’s Complement Output

VCM −VREF/2 VCM + VREF/2 0000 0000 0000 1000 0000 0000 Negative Full-Scale

VCM −VREF/4 VCM + VREF/4 0100 0000 0000 1100 0000 0000

VCM VCM 1000 0000 0000 0000 0000 0000 Mid-Scale

VCM + VREF/4 VCM −VREF/4 1100 0000 0000 0100 0000 0000

VCM + VREF/2 VCM −VREF/2 1111 1111 1111 0111 1111 1111 Positive Full-Scale

Driving the Analog Inputs

The VIN+ and the VIN−inputs of the ADC12DS105 have an internal sample-and-hold circuit which consists of an

analog switch followed by a switched-capacitor amplifier.

Figure 21 and Figure 22 show examples of single-ended to differential conversion circuits. The circuit in

Figure 21 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 22 works well

above 70MHz.

Figure 21. Low Input Frequency Transformer Drive Circuit

Figure 22. High Input Frequency Transformer Drive Circuit

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One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF

transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs

for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the

analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed

to the ADC core.

Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak

excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is

recommended to use VCMO (pins 7,9) as the input common mode voltage.

Reference Pins

The ADC12DS105 is designed to operate with an internal or external 1.2V reference. The internal 1.2 Volt

reference is the default condition when no external reference input is applied to the VREF pin. If a voltage is

applied to the VREF pin, then that voltage is used for the reference. The VREF pin should always be bypassed to

ground with a 0.1 µF capacitor close to the reference input pin.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The Reference Bypass Pins (VRP, VCMO, and VRN) for channels A and B are made available for bypass purposes.

These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor

placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and

VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is

shown in Figure 23. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or

SNR. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should

not be loaded.

Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may

result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance

degradation.

The nominal voltages for the reference bypass pins are as follows:

VCMO = 1.5 V

VRP = 2.0 V

VRN = 1.0 V

OF/DCS Pin

Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,

duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate

a stable internal clock, improving the performance of the part. With OF/DCS = VAthe output data format is 2's

complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset

binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*VAthe output data format is 2's complement

and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*VAthe output data format is offset binary

and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing

this is not recommended as the output data could be erroneous for a few clock cycles after this change is made.

Note: This signal has no effect when SPI_EN is high and the serial control interface is enabled.

DIGITAL INPUTS

Digital CMOS compatible inputs consist of CLK, and PD_A, PD_B, Reset_DLL, DLC, TEST, WAM, SPI_EN,

SCSb, SCLK, and SDI.

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Clock Input

The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input

should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input

signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock

source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and

should not cross any other signal line, analog or digital, not even at 90°.

The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

This is what limits the minimum sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note SNLS035

for information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is

used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(6)

where tPD is the signal propagation rate down the clock line, "L" is the line length and ZOis the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and tPD should be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12DS105 has a Duty Cycle Stabilizer.

Power-Down (PD_A and PD_B)

The PD_A and PD_B pins, when high, hold the respective channel of the ADC12DS105 in a power-down mode

to conserve power when that channel is not being used. The channels may be powered down individually or

together. The data in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass

pins ( VRP, VCMO and VRN ). These capacitors lose their charge in the Power Down mode and must be recharged

by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery

from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance.

Note: This signal has no effect when SPI_EN is high and the serial control interface is enabled.

Reset_DLL

This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become

unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds

after Reset_DLL is asserted.

DLC

This pin sets the output data configuration. With this signal at logic-1, all data is sourced on a single lane

(SD1_x) for each channel. When this signal is at logic-0, the data is sourced on dual lanes (SD0_x and SD1_x)

for each channel. This simplifies data capture at higher data rates.

Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled.

TEST

When this signal is asserted high, a fixed test pattern (101001100011 msb->lsb) is sourced at the data outputs.

When low, the ADC is in normal operation. The user may specify a custom test pattern via the serial control

interface.

Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled.

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WAM

In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this

signal at logic-1 the serial data words are aligned with each other. In single lane mode this pin must be set to

logic-0.

Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled.

SPI_EN

The SPI interface is enabled when this signal is asserted high. In this case the direct control pins (OF/DCS,

PD_A, PD_B, DLC, WAM, TEST) have no effect. When this signal is deasserted, the SPI interface is disabled

and the direct control pins are enabled.

SCSb, SDI, SCLK

These pins are part of the SPI interface. See Serial Control Interface for more information.

DIGITAL OUTPUTS

Digital outputs consist of six LVDS signal pairs (SD0_A, SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS

logic outputs ORA, ORB, DLL_Lock, and SDO.

LVDS Outputs

The digital data for each channel is provided in a serial format. Two modes of operation are available for the

serial data format. Single-lane serial format (shown in Figure 4) uses one set of differential data signals per

channel. Dual-lane serial format (shown in Figure 5) uses two sets of differential data signals per channel in

order to slow down the data and clock frequency by a factor of 2. At slower rates of operation (typically below 65

MSPS) the single-lane mode may be the most efficient to use. At higher rates the user may want to employ the

dual-lane scheme. In either case DDR-type clocking is used. For each data channel, an overrange indication is

also provided. The OR signal is updated with each frame of data.

ORA, ORB

These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in

either high or low direction.

DLL_Lock

When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed

abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL to re-lock

the DLL to the input CLK.

SDO

This pin is part of the SPI interface. See Serial Control Interface for more information.

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AGND

DR GND

ADC12DS105

VDR

3x 0.1 PF

5x 0.1 PF

10 PF

+3.3V

0.1 PF

VIN_B

VINA-

VINA+

0.1 PF

VIN_A

VINB-

VINB+

OF/DCS

CLK

Crystal Oscillator

PD_A

47 29

To capture device (ASIC or FPGA).

Note, all signal pairs should be routed with

100 ohm differential impedance, and should

be terminated with a 100 ohm resistor near

the input of the capture device.

18 pF

AGND

0.1 PF

ADT1-1WT

0.1 PF

VRPA

VRNA

VCMOA

0.1 PF

0.1 PF1 PF

0.1 PF

0.1 PF1 PF

0.1 PF

ADT1-1WT

VCMOB

VRPB

VRNB

VREF

0.1 PF

VDR 26

PD_B

TEST

WAM

SPI_EN

These control pins are

ignored when SPI_EN is high LVDS_Bias 3.6k

FRAME-

SD0_B-

SD0_B+

SD1_B-

SD1_B+

SD0_A-

SD0_A+

SD1_A-

SD1_A+

FRAME+

OUTCLK-

OUTCLK+ 44

SCLK

SDI

SDO 53

SCSb

SPI Interface

+3.0V

ADC12DS105

SNAS382E –SEPTEMBER 2006–REVISED APRIL 2013

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Figure 23. Application Circuit

Serial Control Interface

The ADC12DS105 has a serial interface that allows access to the control registers. The serial interface is a

generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many

microcontrollers and DSP controllers.

The ADC's input clock must be running for the Serial Control Interface to operate. It is enabled when the SPI_EN

(pin 56) signal is asserted high. In this case the direct control pins (OF/DCS, PD_A, PD_B, DLC, WAM, TEST)

have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are

enabled.

Each serial interface access cycle is exactly 16 bits long. Figure 24 shows the access protocol used by this

interface. Each signal's function is described below. The Read Timing is shown in Figure 25, while the Write

Timing is shown in Figure 26

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SCLK

SCSb

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

R/Wb A3 A2 A1 A00 0 0

D7 D6 D5 D4 D3 D2 D1 D0C7 C6 C5 C4 C3 C2 C1 C0

Reserved (3-bits)

(MSB) (LSB)

COMMAND FIELD DATA FIELD

Address (4-bits)

Write DATA

SDI

SDO Hi-Z

D7 D6 D5 D4 D3 D2 D1 D0

(MSB) (LSB)

Data (8-bits)

Read DATA

Single Access Cycle

ADC12DS105

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Figure 24. Serial Interface Protocol

SCLK: Used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the

falling edge. User may disable clock and hold it in the low-state, as long as clock pulse-width min spec is not

violated when clock is enabled or disabled.

SCSb: Serial Interface Chip Select. Each assertion starts a new register access - that is, the SDATA field

protocol is required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted

before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-in

and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement

for the deasserted pulse - which is specified in the Electrical Specifications section.

SDI: Serial Data. Must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long.

R/Wb: A value of '1' indicates a read operation, while a value of '0' indicates

a write operation.

Reserved: Reserved for future use. Must be set to 0.

ADDR: Up to 3 registers can be addressed.

DATA: In a write operation the value in this field will be written to the

operation this field is ignored.

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tSU

Valid Data

tPL tPH

Valid Data

16th clock

SCLK

SDI

tCSH

1st clock

SCLK

8th clock 16th clock

CSb

tCSS tCSH tCSS

tODZ

SDO

tOZD tOD

D7 D0

ADC12DS105

SNAS382E –SEPTEMBER 2006–REVISED APRIL 2013

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SDO: This output is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb assertion,

contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges.

Upon power-up, the default register address is 00h.

Figure 25. Read Timing

Figure 26. Write Timing

Table 2. Device Control Register, Address 0h

76543210

OM DLC DCS OF WAM PD_A PD_B

Reset State : 08h

Bits (7:6) Operational Mode

0 0 Normal Operation.

0 1 Test Output mode. A fixed test pattern (1010011000111msb->lsb) is sourced at the data outputs.

1 0 Test Output mode. Data pattern defined by user in registers 01h and 02h is sourced at data outputs.

1 1 Reserved.

Bit 5 Data Lane Configuration. When this bit is set to '0', the serial data interface is configured for dual-lane mode where the

data words are output on two data outputs (SD1 and SD0) at half the rate of the single-lane interface. When this bit is

set to ‘1’, serial data is output on the SD1 output only and the SD0 outputs are held in a high-impedance state

Bit 4 Duty Cycle Stabilizer. When this bit is set to '0' the DCS is off. When this bit is set to ‘1’, the DCS is on.

Bit 3 Output Data Format. When this bit is set to ‘1’ the data output is in the “twos complement” form. When this bit is set to

‘0’ the data output is in the “offset binary” form.

Bit 2 Word Alignment Mode.

This bit must be set to '0' in the single-lane mode of operation.

In dual-lane mode, when this bit is set to '0' the serial data words are offset by half-word. This gives the least latency

through the device. When this bit is set to '1' the serial data words are in word-aligned mode. In this mode the serial

data on the SD1 lane is additionally delayed by one CLK cycle. (Refer to Figure 5).

Bit 1 Power-Down Channel A. When this bit is set to '1', Channel A is in power-down state and Normal operation is

suspended.

Bit 0 Power-Down Channel B. When this bit is set to '1', Channel B is in power-down state and Normal operation is

suspended.

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Table 3. User Test Pattern Register 0, Address 1h

76543210

Reserved User Test Pattern (13:6)

Reset State : 00h

Bits (7:6) Reserved. Must be set to '0'.

Bits (5:0) User Test Pattern. Most-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in Test

Output Mode.

Table 4. User Test Pattern Register 1, Address 2h

76543210

User Test Pattern (5:0) Reserved

Reset State : 00h

Bits (7:2) User Test Pattern. Least-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in Test

Output Mode.

Bits (1:0) Reserved. Must be set to '0'.

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor

close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.

As is the case with all high-speed converters, the ADC12DS105 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mVP-P.

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12DS105 between these areas, is required to

achieve specified performance.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane area.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors and transformers. Mutual inductance can change the

characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by

side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog

input and the clock input at 90° to one another to avoid magnetic coupling.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

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All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of

the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The

ADC12DS105 should be between these two areas. Furthermore, all components in the reference circuitry and

the input signal chain that are connected to ground should be connected together with short traces and enter the

ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition

region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree

shown in Figure 27. The gates used in the clock tree must be capable of operating at frequencies much higher

than those used if added jitter is to be prevented.

As mentioned inLAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 27. Isolating the ADC Clock from other Circuitry with a Clock Tree

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REVISION HISTORY

Changes from Revision D (April 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 28

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC12DS105CISQ/NOPB ACTIVE WQFN NKA 60 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 12DS105

ADC12DS105CISQE/NOPB ACTIVE WQFN NKA 60 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 12DS105

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Addendum-Page 2

I TEXAS INSTRUMENTS ‘3‘ V.'

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC12DS105CISQ/NOPB WQFN NKA 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1

ADC12DS105CISQE/

NOPB WQFN NKA 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC12DS105CISQ/NOPB WQFN NKA 60 2000 356.0 356.0 35.0

ADC12DS105CISQE/

NOPB WQFN NKA 60 250 208.0 191.0 35.0

Pack Materials-Page 2

mam 77777 =. =. =. =. =. ‘ =. =. =. =. ‘ =. =. =. z. \ Cl \5 a my a 7 , 7 , 7 ‘ 7 , 7 , 7 E DIMENSIONSARK IN MILLIMETKKS =. ‘ =. )wrvsmn m h rm Mm 3w =. =. CI ‘ CI =. \ =. =. ‘ =. W a u! =. ‘ =. =. ifﬂaanaﬂwaamm 77777 a “ ”’4L J L m xteomnnm mm mm“ 7‘ a s W ‘ a \ w 1 Wm an ,Axm um as) c 5101 mﬂl'IHI'II'II'IITII'IHI'IHI'IHm - \UUUULILILIILILILILILILILI 1K I'II'II'IHI'IHI'ImI'IHI'IHI'IIj ’3 L 4L5”- [ L ' TEXAS INSTRUMENTS

MECHANICAL DATA

NKA0060A

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SQA60A (Rev A)

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