74LVC594A-Q100 Datasheet by Nexperia USA Inc.

Datasheet Feedback/Errors

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74LVC594A-Q100

8-bit shift register with output register

Rev. 2 — 21 July 2017 Product data sheet

1 General description

The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a

storage register. Separate clock and reset inputs are provided on both shift and storage

registers.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial Power-down applications using IOFF. The IOFF

circuitry disables the output, preventing the damaging backflow current through the

device when it is powered down.

The shift register has a serial input (DS) and a serial output (Q7S) for cascading

purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in

the shift register is transferred to the storage register on a positive-going transition of the

STCP input. If both clocks are connected together, the shift register is always one clock

pulse ahead of the storage register. A LOW level on one of the two register reset pins

(SHR and STR) clears the corresponding register.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2 Features and benefits

•Automotive product qualification in accordance with AEC-Q100 (Grade 1)

–Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•5 V tolerant inputs/outputs for interfacing with 5 V logic

•Wide supply voltage range from 1.2 V to 3.6 V

•CMOS low-power consumption

•Direct interface with TTL levels

•Balanced propagation delays

•All inputs have Schmitt-trigger action

•Complies with JEDEC standard:

–JESD8-7A (1.65 V to 1.95 V)

–JESD8-5A (2.3 V to 2.7 V)

–JESD8-C/JESD36 (2.7 V to 3.6 V)

•ESD protection:

–MIL-STD-883, method 3015 exceeds 2000 V

–HBM JESD22-A114F exceeds 2 000 V

74LVC594A-Q100 Table 1‘ Ordering information chP STOP — 1A 7 11 7 12 1013 15123A557 SHR STR mbcjw GD 01 02 03 QA 05 Q6 07 "mm

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

2 / 21

3 Applications

•Serial-to-parallel data conversion

•Remote control holding register

4 Ordering information

Table 1. Ordering information

PackageType number

Temperature

range

Name Description Version

74LVC594AD-Q100 -40 °C to +125 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74LVC594APW-Q100 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

74LVC594ABQ-Q100 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

5 Functional diagram

mbc319

STCPSHCP

STRSHR

Q7S

10 13

11 12

Figure 1. Logic symbol

mbc320Q7Q0 Q1 Q2 Q3 Q4 Q5 Q6

SHCP

SHR

STCP

STR

1 2 3 4 5 6 7

8-STAGE SHIFT REGISTER

8-BIT STORAGE REGISTER

Q7S

Figure 2. Functional diagram

74LVC594A-Q100 <7 w7="" w="" [=""> mum

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

3 / 21

mbc321

Q0 Q1 Q2 Q3 Q4 Q5 Q6

SHCP

SHR

STCP

STR

FFSH0

STAGE 0

FFST0

STAGES 1 TO 6

D Q

FFSH7

STAGE 7

FFST7

Q7S

Figure 3. Logic diagram

mbc323

Q7S

STR

SHR

STCP

SHCP

Figure 4. Timing diagram

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Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

4 / 21

6 Pinning information

6.1 Pinning

SHR

74LVC594A-Q100

Q1 VCC

Q2 Q0

Q3 DS

Q4 STR

Q5 STCP

Q6 SHCP

GND Q7S

aaa-009697

Figure 5. Pin configuration SO16 and TSSOP16

STR

aaa-009698

74LVC594A-Q100

Q7 SHR

Q6 SHCP

Q5 STCP

Q3 DS

Q2 Q0

GND

Q7S

Transparent top view

7 10

6 11

5 12

4 13

3 14

2 15

terminal 1

index area

Figure 6. Pin configuration DHVQFN16

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output

GND 8 ground (0 V)

Q7S 9 serial data output

SHR 10 shift register reset (active LOW)

SHCP 11 shift register clock input

STCP 12 storage register clock input

STR 13 storage register reset (active LOW)

DS 14 serial data input

VCC 16 supply voltage

74LVC594A-Q1 00 SHRSTR

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

5 / 21

7 Functional description

Table 3. Function table [1]

Input Output

SHCP STCP SHR STR DS Q7S Qn

Function

X X L X X L NC a LOW-state on SHR only affects the shift register

X X X L X NC L a LOW-state on STR only affects the storage register

X ↑ L H X L L empty shift register loaded into storage register

↑ X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S)

X ↑ H H X NC QnS contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

↑ ↑ H H X Q6S QnS contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

[1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change.

8 Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +6.5 V

IIK input clamping current VI < 0 V -50 - mA

VIinput voltage [1] -0.5 +6.5 V

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

3-state [1] -0.5 6.5 VVOoutput voltage

output HIGH or LOW state [1] -0.5 VCC + 0.5 V

IOoutput current VO = 0 V to VCC - ±50 mA

ICC supply current - 100 mA

IGND ground current -100 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.

For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.

74LVC594A-Q1 00

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

6 / 21

9 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

1.65 - 3.6 VVCC supply voltage

functional 1.2 - - V

VIinput voltage 0 - 5.5 V

3-state 0 - 5.5 VVOoutput voltage

output HIGH or LOW state 0 - VCC V

Tamb ambient temperature -40 - +125 °C

VCC = 1.65 V to 2.7 V - - 20 ns/VΔt/ΔV input transition rise and fall rate

VCC = 2.7 V to 3.6 V - - 10 ns/V

10 Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

VCC = 1.2 V 1.08 - - 1.08 - V

VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC - V

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V

VIH HIGH-level input

voltage

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VCC = 1.2 V - - 0.12 - 0.12 V

VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V

VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V

VIL LOW-level input

voltage

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VI = VIH or VIL

IO = -100 μA;

VCC = 1.65 V to 3.6 V

VCC-0.2 - - VCC-0.3 - V

IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V

IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V

IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V

IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V

VOH HIGH-level output

voltage

IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V

74LVC594A-Q100

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

7 / 21

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

VI = VIH or VIL

IO = 100 μA;

VCC = 1.65 V to 3.6 V

- - 0.2 - 0.3 V

IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V

IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V

IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V

VOL LOW-level output

voltage

IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V

IIinput leakage

current

VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA

IOFF power-off leakage

current

VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 μA

ICC supply current VCC = 3.6 V;

VI = VCC or GND; IO = 0 A

- 0.1 10 - 40 μA

ΔICC additional supply

current

per input pin;

VCC = 1.65 V to 3.6 V;

VI = VCC - 0.6 V; IO = 0 A

- 5 500 - 5000 μA

CIinput capacitance VCC = 0 V to 3.6 V;

VI = GND to VCC

- 5.0 - - - pF

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.

74LVC594A-Q100 Figure 13 Figure 7 Figure B Figure 11 Figure 12

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

8 / 21

11 Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

SHCP to Q7S; see Figure 7 [2] [3]

VCC = 1.2 V - 17.5 - - - ns

VCC = 1.65 V to 1.95 V 2.0 5.2 15.8 2.0 18.2 ns

VCC = 2.3 V to 2.7 V 1.5 3.2 8.1 1.5 9.3 ns

VCC = 2.7 V 1.5 3.5 7.6 1.5 8.7 ns

VCC = 3.0 V to 3.6 V 1.5 3.1 6.7 1.5 7.7 ns

STCP to Qn; see Figure 8 [2]

VCC = 1.2 V - 19.3 - - - ns

VCC = 1.65 V to 1.95 V 2.0 7.6 15.8 2.0 18.2 ns

VCC = 2.3 V to 2.7 V 1.5 4.8 8.1 1.5 9.3 ns

VCC = 2.7 V 1.5 5.2 7.6 1.5 8.7 ns

tpd propagation delay

VCC = 3.0 V to 3.6 V 1.2 4.5 6.7 1.2 7.7 ns

SHR to Q7S; see Figure 11

VCC = 1.2 V - 12.0 - - - ns

VCC = 1.65 V to 1.95 V 2.0 5.0 15.8 2.0 18.2 ns

VCC = 2.3 V to 2.7 V 1.5 3.8 8.1 1.5 9.3 ns

VCC = 2.7 V 1.2 3.9 7.6 1.2 8.7 ns

VCC = 3.0 V to 3.6 V 1.2 3.3 6.7 1.2 7.7 ns

STR to Qn; see Figure 12

VCC = 1.2 V - 20.0 - - - ns

VCC = 1.65 V to 1.95 V 2.0 7.7 15.8 2.0 18.2 ns

VCC = 2.3 V to 2.7 V 1.5 5.0 8.1 1.5 9.3 ns

VCC = 2.7 V 1.2 5.3 7.6 1.2 8.7 ns

tPHL HIGH to LOW

propagation delay

VCC = 3.0 V to 3.6 V 1.2 4.4 6.7 1.2 7.7 ns

74LVC594A-Q1 00 CP, STCP GH or L0 Figure 7 Figure 3 SHR, STR LO Figure 11 Figure 12

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

9 / 21

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

SHCP, STCP HIGH or LOW;

see Figure 7 and Figure 8

VCC = 1.65 V to 1.95 V 6.0 2.5 - 7.0 - ns

VCC = 2.3 V to 2.7 V 5.0 2.0 - 5.5 - ns

VCC = 2.7 V 4.5 1.5 - 5.0 - ns

VCC = 3.0 V to 3.6 V 4.0 1.5 - 4.5 - ns

SHR, STR LOW;

see Figure 11 and Figure 12

VCC = 1.65 V to 1.95 V 6.0 2.5 - 5.5 - ns

VCC = 2.3 V to 2.7 V 4.0 2.0 - 4.5 - ns

VCC = 2.7 V 2.5 1.5 - 3.0 - ns

tWpulse width

VCC = 3.0 V to 3.6 V 2.5 1.5 - 3.0 - ns

DS to SHCP; see Figure 9

VCC = 1.65 V to 1.95 V 5.0 1.0 - 5.5 - ns

VCC = 2.3 V to 2.7 V 4.0 0.8 - 4.5 - ns

VCC = 2.7 V 2.0 0.6 - 2.5 - ns

VCC = 3.0 V to 3.6 V 2.0 0.6 - 2.5 - ns

SHR to STCP; see Figure 10

VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns

VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns

VCC = 2.7 V 4.0 1.8 - 4.5 - ns

VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns

SHCP to STCP; see Figure 8

VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns

VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns

VCC = 2.7 V 4.0 1.8 - 4.5 - ns

tsu set-up time

VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns

DS to SHCP; see Figure 9 [3]

VCC = 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns

VCC = 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns

VCC = 2.7 V 1.5 -0.1 - 2.0 - ns

thhold time

VCC = 3.0 V to 3.6 V 1.0 -0.2 - 1.5 - ns

74LVC594A-Q100 SF“? in SHCP STR (0 STOP Figure 11 Figure 12 Figure 7 Figure 3

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

10 / 21

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

SHR to SHCP, STR to STCP;

see Figure 11 and Figure 12

VCC = 1.65 V to 1.95 V 5.0 -2.7 - 5.5 - ns

VCC = 2.3 V to 2.7 V 4.0 -1.5 - 4.5 - ns

VCC = 2.7 V 2.0 -1.0 - 2.5 - ns

trec recovery time

VCC = 3.0 V to 3.6 V 2.0 -1.0 - 2.5 - ns

SHCP or STCP; see Figure 7

and Figure 8

VCC = 1.65 V to 1.95 V 80 130 - 70 - MHz

VCC = 2.3 V to 2.7 V 100 140 - 90 - MHz

VCC = 2.7 V 110 150 - 100 - MHz

fmax maximum

frequency

VCC = 3.0 V to 3.6 V 130 180 - 115 - MHz

tsk(o) output skew time VCC = 3.0 V to 3.6 V [4] - - 1.0 - 1.5 ns

VI = GND to VCC

[5]

VCC = 1.65 V to 1.95 V - 50 - - - pF

VCC = 2.3 V to 2.7 V - 45 - - - pF

CPD power dissipation

capacitance

VCC = 3.0 V to 3.6 V - 44 - - - pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] Cascadability is guaranteed under identical VCC and temperature conditions.

[4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC

2 x fi x N + ∑(CL x VCC

2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL x VCC

2 x fo) = sum of outputs.

74LVC594A-Q100 mma559

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

11 / 21

12 Waveforms and test circuit

mna557

SHCP input

Q7S output

tPLH tPHL

1/fmax

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and

maximum shift clock frequency

mna558

STCP input

Qn output

tPLH tPHL

tsu 1/fmax

VOH

GND

VOL

SHCP input

GND

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width

and the shift clock to storage clock set-up time

74LVC594A-Q100 mnasan Table 8 ﬂ NP 2! rub-r325 Table 8 (W

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

12 / 21

mna560

GND

tsu

VOH

VOL

Q7S output

SHCP input

DS input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 9. The data set-up and hold times for the serial data input (DS)

mbc326

tsu

STCP input

Qn outputs

SHR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 10. The shift reset (SHR) to storage clock (STCP) set-up times

74LVC594A-Q100 SHR _\ % E m 324 Table 8 (W mb5325 Table 8 (STR

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

13 / 21

mbc324

tPHL

trec

SHCP input

Q7S output

SHR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the

shift reset to shift clock (SHCP) recovery time

mbc325

tPHL

trec

STCP input

Qn outputs

STR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Figure 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays

and the storage reset to storage clock (STCP) recovery time

Table 8. Measurement points

Supply voltage Input Output

VCC VMVM

VCC < 2.7 V 0.5 x VCC 0.5 x VCC

VCC ≥ 2.7 V 1.5 V 1.5 V

74LVC594A-Q100

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

14 / 21

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Test data is given in Table 9. Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Figure 13. Test circuit for measuring switching times

Table 9. Test data

Input Load VEXT

Supply voltage

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 x VCC GND

1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 x VCC GND

2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 x VCC GND

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 x VCC GND

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 x VCC GND

74LVC594A-Q100 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 ‘— —. <7 :l="" .-="" ’l="" hmhhhhhh="" ,l,="" ,="" ,="" j="" a="" gh—‘p="" h="" w:="" hhlhljhhhﬂ.="">

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

15 / 21

13 Package outline

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpc D(1) E(1) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Figure 14. Package outline SOT109-1 (SO16)

74LVC594A-Q100 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 «7 4» Ci x): m J‘:gg ll ‘ ‘ L7 J/ 5-- T “‘iHHHiHHHF 1 V1: OX 1 i + $ He J WSW H Hi- Ea

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

16 / 21

UNIT A1A2A3bpc D (1) E(2) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.40

0.06

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

1 8

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Figure 15. Package outline SOT403-1 (TSSOP16)

74LVC594A-Q100 DHVQFN1G: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; ‘—~H D l 1 A , ~ ***** i» ***** ~ :e mi: % :1 l ":1; El FD » BF 1 ‘kg 80 l l mm r» «mm ;wwupuu T D ‘ 4&4 iiﬁifiéé§ 7%\ l ‘/ \ ﬂmmmmm \ /

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

17 / 21

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

detail X

y1C

2 7

15 10

B A

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Figure 16. Package outline SOT763-1 (DHVQFN16)

74LVC594A-Q100 Table 10. Abbreviations Table 11. Revision history Table 7

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

18 / 21

14 Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MIL Military

TTL Transistor-Transistor Logic

15 Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC594A_Q100 v.2 20170721 Product data sheet - 74LVC594A_Q100 v.1

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Table 7: table note added for cascading purposes.

74LVC594A_Q100 v.1 20131115 Product data sheet - -

74LVC594A-Q100 Ince mis dacumenl was pu mg llwww neggenamm

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

19 / 21

16 Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local Nexperia

sales office. In case of any inconsistency or conflict with the short data sheet,

the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory. Notwithstanding any damages that

customer might incur for any reason whatsoever, Nexperia's aggregate and

cumulative liability towards customer for the products described herein shall

be limited in accordance with the Terms and conditions of commercial sale of

Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification. Customers are responsible for the

design and operation of their applications and products using Nexperia

products, and Nexperia accepts no liability for any assistance with

applications or customer product design. It is customer’s sole responsibility

to determine whether the Nexperia product is suitable and fit for the

customer’s applications and products planned, as well as for the planned

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products. Nexperia does not accept

any liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using Nexperia products in order to avoid a default of the

applications and the products or of the application or use by customer’s third

party customer(s). Nexperia does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This Nexperia product

has been qualified for use in automotive applications. Unless otherwise

agreed in writing, the product is not designed, authorized or warranted to

be suitable for use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction of an Nexperia

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. Nexperia and its suppliers accept

no liability for inclusion and/or use of Nexperia products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

74LVC594A-Q100

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Product data sheet Rev. 2 — 21 July 2017

20 / 21

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74LVC594A-Q100

Nexperia 74LVC594A-Q100

8-bit shift register with output register

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 21 July 2017

Document identifier: 74LVC594A_Q100

Contents

1 General description ............................................ 1

2 Features and benefits .........................................1

3 Applications .........................................................2

4 Ordering information .......................................... 2

5 Functional diagram ............................................. 2

6 Pinning information ............................................ 4

6.1 Pinning ............................................................... 4

6.2 Pin description ................................................... 4

7 Functional description ........................................5

8 Limiting values ....................................................5

9 Recommended operating conditions ................ 6

10 Static characteristics .......................................... 6

11 Dynamic characteristics .....................................8

12 Waveforms and test circuit .............................. 11

13 Package outline .................................................15

14 Abbreviations .................................................... 18

15 Revision history ................................................ 18

16 Legal information .............................................. 19

74LVC594A-Q100 Datasheet by Nexperia USA Inc.

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