MJD148T4(G), NJVMJD148T4G Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 9 1Publication Order Number:
MJD148/D
MJD148
NPN Silicon Power
Transistor
DPAK for Surface Mount Applications
Designed for general purpose amplifier and low speed switching
applications.
Features
•High Gain
•Low Saturation Voltage
•High Current Gain − Bandwidth Product
•Epoxy Meets UL 94 V−0 @ 0.125 in
•NJV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector−Emitter Voltage VCEO 45 Vdc
Collector−Base Voltage VCB 45 Vdc
Emitter−Base Voltage VEB 5.0 Vdc
Collector Current − Continuous IC4.0 Adc
Collector Current − Peak ICM 7.0 Adc
Base Current IB50 mAdc
Total Power Dissipation
@ TC = 25°C
Derate above 25°C
PD20
0.16 W
W/°C
Total Power Dissipation (Note 1)
@ TA = 25°C
Derate above 25°C
PD1.75
0.014 W
W/°C
Operating and Storage Junction
Temperature Range TJ, Tstg −55 to +150 °C
ESD − Human Body Model HBM 3B V
ESD − Machine Model MM C V
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
POWER TRANSISTOR
4.0 AMPERES
45 VOLTS, 20 WATTS
MARKING DIAGRAM
A = Assembly Location
Y = Year
WW = Work Week
J148 = Device Code
G = Pb−Free Package
Device Package Shipping†
ORDERING INFORMATION
DPAK
CASE 369C
STYLE 1
www.onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
AYWW
J148G
MJD148T4G DPAK
(Pb−Free) 2,500/Tape & Ree
l
NJVMJD148T4G DPAK
(Pb−Free) 2,500/Tape & Ree
l
3
2
1
4
1
BASE
3
EMITTER
COLLECTOR
2, 4
MJD148
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction−to−Case RqJC 6.25 °C/W
Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 71.4 °C/W
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
ELECTRICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 3)
(IC = 100 mAdc, IB = 0) VCEO(sus) 45 − Vdc
Collector Cutoff Current
(VCB = 45 Vdc, IE = 0) ICBO − 20 mAdc
Emitter Cutoff Current
(VBE = 5 Vdc, IC = 0) IEBO − 1 mAdc
ON CHARACTERISTICS (Note 3)
DC Current Gain
(IC = 10 mAdc, VCE = 5 Vdc)
(IC = 0.5 Adc, VCE = 1 Vdc)
(IC = 2 Adc, VCE = 1 Vdc)
(IC = 3 Adc, VCE = 1 Vdc)
hFE 40
85
50
30
−
375
−
−
−
Collector−Emitter Saturation Voltage
(IC = 2 Adc, IB = 0.2 Adc) VCE(sat) − 0.5 Vdc
Base−Emitter On Voltage
(IC = 2 Adc, VCE = 1 Vdc) VBE(on) − 1.1 Vdc
DYNAMIC CHARACTERISTICS
Current−Gain−Bandwidth Product
(IC = 250 mAdc, VCE = 1 Vdc, f = 1 MHz) fT3 − MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5°C OU‘C 11 \ W W 1 0‘0
MJD148
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3
TYPICAL CHARACTERISTICS
Figure 1. DC Current Gain
IC, COLLECTOR CURRENT (A)
hFE, DC CURRENT GAIN
0.001 0.01 0.1 1 10
VCE = 1 V
150°C
−55°C
25°C
10
100
10000
1000 100°C
Figure 2. DC Current Gain
IC, COLLECTOR CURRENT (A)
hFE, DC CURRENT GAIN
0.001 0.01 0.1 1 10
VCE = 10 V
150°C
−55°C
25°C
10
100
10000
1000 100°C
Figure 3. Collector Saturation Region
IB, BASE CURRENT (mA)
2
0
0.05
1.6
1.2
0.1 1 2 3 5 10 20 30 500
0.8
0.4
0.07 0.2 0.50.3
TJ = 25°C
IC = 10 mA
0.7 7 50 70 100 200 300
100 mA 1 A 3 A
VCE, COLLECTOR−EMITTER VOLTAGE (V)
Figure 4. Base Emitter Voltage vs. Collector
Current Figure 5. Base Emitter Saturation Voltage vs.
Collector Current
IC, COLLECTOR CURRENT (A)
VBE(sat), BASE−EMITTER
SATURATION VOLTAGE (V)
0.001 0.01 0.1 1 1
0
IC/IB = 10
150°C
TA = −55°C
25°C
0
0.6
1.2
100°C
0.00010.000010.000001
0.2
0.8
0.4
1.0
IC, COLLECTOR CURRENT (A)
V
BE(on)
, BASE−EMITTER VOLTAGE (V)
0.001 0.01 0.1 1 10
VCE = 2 V
150°C
TA = −55°C
25°C
0
0.6
1.2
100°C
0.00010.00001
0.2
0.8
0.4
1.0
0.0 S‘NGLE PULSE
MJD148
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4
Figure 6. Collector Emitter Saturation Voltage
vs. Collector Current
IC, COLLECTOR CURRENT (A)
Figure 7. Temperature Coefficients
+2.5
IC, COLLECTOR CURRENT (A)
0.005 0.01 0.020.030.05 0.1 0.5 10.20.3 2 3
+2
+1.5
+1
0
−0.5
−1
−1.5
−2
+0.5
−2.5
*APPLIES FOR IC/IB ≤ hFE/2
*TJ = −65°C to +150°C
*qV for VCE(sat)
qV for VBE
qy, TEMPERATURE COEFFI-
CIENTS (mV/°C)
4
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
0.001 0.01 0.1 1 10
IC/IB = 10
150°C
TA = −55°C
25°C
0
0.15
0.5
0.3
100°C
0.00010.000010.000001
0.5
0.2
0.35
0.1
0.25
0.4
0.45
103
−0.4
Figure 8. Collector Cut−Off Region
VBE, BASE−EMITTER VOLTAGE (V)
101
10−3
102
100
10−1
10−2
−0.3 −0.2 −0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6
REVERSE FORWARD
TJ = 150°C
VCE = 30 V
100°C
25°C
ICES
Figure 9. Thermal Response
t, TIME (ms)
1
0.01
0.01
0.5
0.2
0.1
0.05
0.02
0.05 1 2 5 10 20 50 100 200 1
k
500
ZqJC(t) = r(t) RqJC
RqJC = 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) ZqJC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
D = 0.5
0.2
0.05
0.01
SINGLE PULSE
0.1
0.7
0.3
0.07
0.03
0.02 0.1 0.50.2
IC, COLLECTOR CURRENT (mA)
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
MJD148
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5
10
1
Figure 10. Maximum Rated Forward Bias
VCE, COLLECTOR−EMITTER VOLTAGE (V)
5
3
2
0.5
0.01 510
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
IC, COLLECTOR CURRENT (A)
dc
500 ms
0.3
0.05
23
1ms
20 30 50 70
1
0.2
7
0.1
0.03
0.02 TC = 25°C SINGLE PULSE, D ≤ 0.1%
TJ = 150°C
5ms
Forward Bias Safe Operating Area Information
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 10 is based on TJ(pk) = 150°C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided TJ(pk)
≤ 150°C. TJ(pk) may be calculated from the data in Figure 9.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the
limitations imposed by second breakdown.
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DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
12
3
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4
b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
e
BOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DPAK (SINGLE GAUGE)
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