TP11362A Datasheet by Texas Instruments

yNational Semiconductor TP11362A March 1997 Quad Adaptive Differential PCM Processor General Description The TPHSSZA is a quad (A) channei Adapnve DMevenhai Poise Cede Meduiaucn {ADPCMJ \ranscoaen My compair iblE \o iTU G726 vecommendauon m 413kbps 32 kbps‘ 2A Maps 16 khps and ANS‘ 32 kbps modes The TPH 362A ADPCM processor can operate on up |0 a maependem channels m an 8 kHz lrame Each channel is indwlduaHy canngureu, supporting bmh mu and nan dupiex epevahon AH mpuuempm (ransiers occur on an Imevrupt basrs usmg ser Hat doubie buWered data vegis|evs Together wnh Nailonai‘s TP3054’57 COMBOE or TP307DH1 COMBO || GEVICES‘ \he TPHSSZA ﬁorms compleie ADPCM ohanneis wuh Cadet! unenng Features - ccrrr G 726 compahbie a\ «0‘ 32‘ 24‘ 16 kbps - ANSI T1 301 oompahbie a| 32 kbps - Erchannel haiﬁrdupiex (encode m decade) or Archannei luHrdupiex operahon m 8 kHz name Each channel individually conﬁgurable Seiemable urlaw 0r Maw PcM ceding Asynchronous 5 MHz masier clock aperauen TrL and cMos cempaume mpms and empms 287mm FLCC or 2Arpm DiP packages Power consumption or in) 6 mW a| .sv per ﬁuilrduplex ohannei Oanhip PowerrOnrHeset - rAD’C m +85’C epevaimg \emperamre range - Singie 5v suppiy Block Diagram W Pm mm mm” mm m mm Pros-55m w ADPCM mm mm, away m m r56» ASEK emu UMP“ Mew m ASCK m amp-A may W50 mu Pscx comm sme mum: FIGURE 1. Block Diagram w amp and coMaov are new ”mm a! mm sewnmnunmrcmvmxhnn 40339904d INOd lenuaiama anndepv peno VZQELLdl

TP11362A

Quad Adaptive Differential PCM Processor

General Description

The TP11362A is a quad (4) channel Adaptive Differential

Pulse Code Modulation (ADPCM) transcoder, fully compat-

ible to ITU G.726 recommendation in 40 kbps, 32 kbps,

24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11362A

ADPCM processor can operate on up to 8 independent

channels in an 8 kHz frame. Each channel is individually

configured, supporting both full and half duplex operation. All

input/output transfers occur on an interrupt basis using se-

rial, double buffered data registers. Together with National’s

TP3054/57 COMBO®or TP3070/71 COMBO II devices, the

TP11362A forms complete ADPCM channels with Codec/

filtering.

Features

nCCITT G.726 compatible at 40, 32, 24, 16 kbps

nANSI T1.301 compatible at 32 kbps

n8-channel half-duplex (encode or decode) or 4-channel

full-duplex operation in 8 kHz frame

nEach channel individually configurable

nSelectable µ-law or A-law PCM coding

nAsynchronous 8 MHz master clock operation

nTTL and CMOS compatible inputs and outputs

n28-pin PLCC or 24-pin DIP packages

nPower consumption of typ. 6 mW at +5V per full-duplex

channel

nOn-Chip Power-On-Reset

n−40˚C to +85˚C operating temperature range

nSingle 5V supply

Block Diagram

TRI-STATE®and COMBO®are registered trademarks of National Semiconductor Corporation.

DS012877-1

FIGURE 1. Block Diagram

March 1997

TP11362A Quad Adaptive Differential PCM Processor

Connection Diagrams Plaetlc chlp Carrlers t s 2 t 22 27 25 NC 25 —PCMt rsr2 2t — rsta tsvt 2: —ttsva RSt TPII362AV 12 —C[ rsa 2t —m ASCK zo ttttt ELK ta —rtt t2 t1 U ts t5 t7 ‘8 NE NB the WIN amt Top Vlew order Number TPmezAv see us Package Number VZBA Pin Descrlphons Tsl Transmtt PCM senal data tnput Tst ts an Brbtl PcM data stream and ts shttted tnto an Erbt‘ sertatrlnrparattet regtster on the latttng edges ot FSCK whtte CE and THE are htgh The last a btrs ol Tst are latohed and ttanslerred to the core tor prooesstng at the latttng edge ot CE, Tso Transmtt ADPcM THLSTATE“ sertat data output, A sertat data btt stream ot 47 to Srbtl tength ts shttted out wtth the “Sr tng edge ot ASCK when CE ts htgh lottowtng the prooesstng at a transmtt channet, Tso ts tn TRIVSTATE mode whtte CE ts tow or whtte H50 output ts aclttle RSI Hecetve ADPcM sertat data tnput. A sertat data btt strearn ol Ar to ﬁrblt tength ts shttted tn wtth the latttng edges MASCK whtte CE ts htgh and THE ts tow The last A or 5 btts ol RSI are tatohed and transterred to the core tot prooesstng at the latttng edge at GE. nso Hecetve Pct/t TRLSTATE sertat data output. An Srbtt sertat PcM data stream ts shttted out wtth the rtstng edges ol PsoK when CE ts htgh lottowtng the prooesstng ot a Vecettle ohannet HSO ts tn TRLSTATE mode whtte CE ts tow orwhtte TSO output ts acttve. FSCK PcM sertat clack tnput. PSCK ts used to shtlt PCM data tnto Tst or out ot H50 whtte CE ts aotwe thtgh) The transter de pends on the logto state ot THE. ASCK ADPCM senat clack tnput ASCK ts used to shttt ADPCM data tnto RSt or out at TSO whtte CE ts acttve (htgh). The transter depends on the togto state at THE Plastlc Dual-ln»Llne GNDZ— t 2t —VCEY wscn— 2 25 —nso rst— 3 22 —ht, rst2— ¢ 2t 4th tstt— 5 20 —rstq Rst— 5 t9 —ttsro TF11362AN Tsu— 7 to —C[ ASCK- 5 t7 —EN ELK— s ts —tNH rnta— to t5 —'JSEU7 NC— tt tt —osnt BNDt—tz tS—tcrz Top vtew order Number TPtuezAN see Ns Package Number NMA CLK Master clock tnput CLK may be asynchronous to PsoK or Asch. CE chtp enabte tnput wnen CE ts htgh, tt enabtes data transter. The latttng edge ol CE latches and transters the sertat data Tst or RSI to the core lor prooesstng and strobes the control stgnats QSELD, QSELt, Pth. EN and lNlT, CE should change state only when PSCK and ASCK are htgh. CE. when low, sets the T50 and R50 outputs tnto THLSTATE rnode, THB Transmttter or teoetuet seleot. A logto tow at THE selects the recetver ot the ohannet processed A logto htgh enables the transrntttet ol the ohannet processed. THE detetmtnes whtoh tnput regtster ts enabled and whtoh output regtster and out put ts enabled. TRB should be stable whtte CE ts htgh. EN channel enabte tnput, EN ts strobed tn wtth the latttng edge ot CE. A togto htgh at the latttng edge ot CE tndtoates that the ohannet ts acttve. and the ADFCM wtll process the data tust otoohed tn INIT channel tntttattzatton tnput thT ts read at the latttng edge at GE A togto htgh at the latttng edge at GE causes the ADPCM processor to tntttattze the ohannet currently ptooesstng. Pom Pom oodtng taw seteot A logto tow at Pth setects Brbt| urtawt whtte a togto htgh seteors SrbtlArlaw wtth even btt m7 yerston.

Connection Diagrams

Pin Descriptions

TSI

Transmit PCM serial data input. TSI is an 8-bit PCM data

stream and is shifted into an 8-bit serial-to-parallel register

on the falling edges of PSCK while CE and TRB are high.

The last 8 bits of TSI are latched and transferred to the core

for processing at the falling edge of CE.

TSO

Transmit ADPCM TRI-STATE®serial data output. A serial

data bit stream of 4- to 5-bit length is shifted out with the ris-

ing edge of ASCK when CE is high following the processing

of a transmit channel. TSO is in TRI-STATE mode while CE

is low or while RSO output is active.

RSI

Receive ADPCM serial data input. A serial data bit stream of

4- to 5-bit length is shifted in with the falling edges of ASCK

while CE is high and TRB is low. The last 4 or 5 bits of RSI

are latched and transferred to the core for processing at the

falling edge of CE.

RSO

Receive PCM TRI-STATE serial data output. An 8-bit serial

PCM data stream is shifted out with the rising edges of

PSCK when CE is high following the processing of a receive

channel. RSO is in TRI-STATE mode while CE is low or while

TSO output is active.

PSCK

PCM serial clock input. PSCK is used to shift PCM data into

TSI or out of RSO while CE is active (high). The transfer de-

pends on the logic state of TRB.

ASCK

ADPCM serial clock input. ASCK is used to shift ADPCM

data into RSI or out of TSO while CE is active (high). The

transfer depends on the logic state of TRB.

CLK

Master clock input. CLK may be asynchronous to PSCK or

ASCK.

Chip enable input. When CE is high, it enables data transfer.

The falling edge of CE latches and transfers the serial data

TSI or RSI to the core for processing and strobes the control

signals QSEL0, QSEL1, PCM1, EN and INIT. CE should

change state only when PSCK and ASCK are high. CE,

when low, sets the TSO and RSO outputs into TRI-STATE

mode.

TRB

Transmitter or receiver select. A logic low at TRB selects the

receiver of the channel processed. A logic high enables the

transmitter of the channel processed. TRB determines which

input register is enabled and which output register and out-

put is enabled. TRB should be stable while CE is high.

Channel enable input. EN is strobed in with the falling edge

of CE. A logic high at the falling edge of CE indicates that the

channel is active, and the ADPCM will process the data just

clocked in.

INIT

Channel initialization input. INIT is read at the falling edge of

CE. A logic high at the falling edge of CE causes the ADPCM

processor to initialize the channel currently processing.

PCM1

PCM coding law select. A logic low at PCM1 selects 8-bit

µ-law, while a logic high selects 8-bit A-law with even bit in-

version.

Plastic Chip Carriers

DS012877-2

Top View

Order Number TP11362AV

See NS Package Number V28A

Plastic Dual-In-Line

DS012877-3

Top View

Order Number TP11362AN

See NS Package Number N24A

www.national.com 2

Pin Descrip ons (Cnnhnued) nsELa, QSELI ADPCM btt rate setect tnputs. Ttte OSELO and use stgnats are strobed tn VII“! the tatttng edge at CE. The OSELD and OSEU setect the converston btt rate at the PCM data tust ctcctred tn at the Tst tnput or the btt rate ot the ADFCM data tust mocked tn at the ﬁst tnput. see Tab/e 1. RSTE chtp reset tnput, A tow tc htgtt transtttcn at RSTB tntttates the reset sequence whtoh tntttattzes the channet yartabtes tor att elgh| channets A togtc tcw apptted to thts ptn sets the transccder tnto a tow power dtsstpattcn mode HSTE shcutd be putted htgtt tar normat operattcn TsTa. TsTt, TsT2 Test tnputs tor tactory testtng purposes. TSTOrZ shcutd be tted tcw tor normat cperatton Vccu Vcca chtltve powet suppty tnput ptns. vcc _ 5v 15%, A 0.1 uF ceramtc bypass capacttcr shcutd be ccnnected between vcm and GNDI‘ and vCCZ and GND2 cum, (3an Ground tnput ptns No Net cannected Functional Desc ptton Adaphve DtWerenltaT Pu‘se Code Modulamn (ADPCM) ts a transccdtng atgbrtthtn tar vctce and Vmce band data transr mtsston The use D! ADPCM reduces \he channel handwtmh regutretnents Item the standard 64 kbps PCM stgnat by a tactor at Mo or more, It ts used tar converttng a 64 kbps AVTaw Dr “Jaw FCM channe‘ (D and ham 3 ‘0‘ 32, 24 Dr 16 kbps channeL The ﬁrm PCM stgna‘ ts teduced (D 275 ms ADPCM stgnat dependtng an the setected btt rate tn the em cadet The TPt 1 362A meels the ITU (CCITT) G 726 tecammehdar (tun tar 40‘ 32‘ 2k and 16 kbps ADPCMt as we“ as ANST T1 301 Var 32 khps Each channe‘ can he Operated wtlh an tndependentty setectabte btt rate detenntned by OSELI and OSELD tsee Tab/e 1) TABLE I. an Rate Selection nsELt osELn ADPCM Btt Rate a o 32 khps o t 2s khps t 0 ts khps t t 40 khps The ADPCM enccder converts the 64 kbps Maw cr Maw FCM tnput stgnat to a unttcrtn FCM stgnat whtch ts subr tracted trctn an esttmated stgnat cbtatned trctn an adaptwe predtctcr. A 317‘ tart 77, cr Met/el nonruntimm ouanttzer ts used ta asstgn Twat tour, three or two btnary dtgtts, respecr (Ivelyt to the yatue at the dttterence stgnat tor transmtsstcn. The ADPCM decoder reconstructs the ortgtnat POM stgnat by addtng ttte recetyed guanttzed stgnat tc the stgnat esltmar ttcn catcutated by the predtotor A synchroncus ccdtng adr tusttnent untt prevents cumutattye dtstcrtton occurrtng an syncttrcnous tandem ccdtngs (ADFCMVPCMVADFCM) unr der certatn condtttcns. The adaptwe predtctcr ccnststs ct twc tndependent predtctcr structures. one uses a second order recurstye tttter wtttctt modets ttte potes, and the other uses a stx|h order nonrrecutstve tttter wtttch modets the zeros tn the tnput STgr nat Thts duat structure enabtes ehecttue handttng ot bctn speech and yotce band data stgnats, ADPCM PROCESSING ADPCM to PCM Deccdtttg Operation When a togtc “0 at THE ts tatched tn wtth the tatttng edge at ca the ADPcM processcr ts set ta the decodtng mode Data apptted at the ﬁst tnput ts sampted wtth the tatttng edge at ASCK tnto a 57th ADPCM sertat regtster. thhtn the nex| cycte at GE ttte deccder convens ttte ADPCM tnput data to an 87th cctnpanded FCM data atter t23 master clocks (CLK). The 87b“ parattet PCM data ts tcaded tnto a paraHeHorsertaT sttttt regtster and shttted cut at the H50 out put wtth the rtstng edges ot PSCK POM to ADPCM Enccdtng Operatton A togtc "1" at THE at the tatttng edge at GE sets the ADPCM processcr to the enccdtng tncde. Data apptted at the TSI Tm put ts satnpted tn an tnternat 87b“ PCM regtsterwtth the tallr tng edge at PSCK. Durtng the hex\ cycte ot CE‘ the encoder ccnuerts the cctnpanded 87th PCM data tntc a 57, ,37 cr 27bt|ADPCM data whtch wttt be sttttted out dunno the thtrd cycte ot CE at the T50 cutputwtttt ttte nstng edges ct AscK. The TPttaszA regutres cne master clock stgnat CLK The master ctcck stgnat th< ts="" nct="" reoutred="" tc="" be="" syncttrcnous="" to="" the="" sertat="" i/o="" duels="" asck="" cr="" psck="" the="" sertat="" tntertace="" uses="" the="" sertat="" slacks="" asck="" and="" psck="" and="" chtp="" enabte="" ce="" tar="" recetutng="" and="" transtnttttng="" data="" the="" data="" ts="" tnternatty="" syncttrcntzed="" tc="" the="" master="" ctcck="" clk="" there="" ts="" a="" tcwer="" tttntt="" at="" the="" ctccktreouency="" tar="" clk="" resutttng="" trcm="" the="" number="" at="" ctcck="" cyctes="" reoutred="" tcr="" prccesstng="" the="" data="" table="" 2sttows="" the="" regutred="" ctcctr="" cyctes="" per="" channet="" dependtng="" on="" the="" ser="" tected="" mode,="" table="" 2.="" processtng="" cyctes="" mode="" 0!="" operatton="" clk="" cyctes="" needed="" decoder="" 123="" encoder="" 123="" tntttattzed="" channet="" «5="" dtsabted="" channet="" 4="" the="" sampltng="" pertcd="" (usuatty="" t25="" us="" tcr="" 8="" khz="" tramet="" dtytded="" by="" the="" number="" at="">< cyctes="" gtyes="" the="" regutred="" tntnttnutn="" clk="" pertod.="" a="" sttgtttty="" htgher="" clk="" treouency="" ts="" used="" tn="" order="" tc="" attow="" tor="" tttter="" and="" tnaccuractes="" tn="" the="" clk="" rate,="" as="" an="" ex="" ampte.="" tor="" a="" tour="" channet="" adpcm="" codec="" clk="" treguency="" ts="" 5="" mhz="" as="" sttown="" tn="" the="" tcttcwtng="" catcutattcns="" tclk="125" us="" he="" ‘123)="127,03" ns="" tmm="t/tcLK" a="" 7572="" mhz="" tam”="" a="" a="" 0="" mhz="" the="" pertod="" at="" ge="" must="" be="" eguat="" ta="" cr="" greater="" than="" the="" 127="" qutred="" number="" at="" clk="" cyctes="" tunes="" the="" pertod="" ot="" clk="" ce="" must="" be="" tcw="" tor="" more="" than="" 4="">< cyctes,="">

Pin Descriptions (Continued)

QSEL0, QSEL1

ADPCM bit rate select inputs. The QSEL0 and QSE1 signals

are strobed in with the falling edge of CE. The QSEL0 and

QSEL1 select the conversion bit rate of the PCM data just

clocked in at the TSI input or the bit rate of the ADPCM data

just clocked in at the RSI input. See

Table 1

RSTB

Chip reset input. A low to high transition at RSTB initiates the

reset sequence which initializes the channel variables for all

eight channels. A logic low applied to this pin sets the

transcoder into a low power dissipation mode. RSTB should

be pulled high for normal operation.

TST0, TST1, TST2

Test inputs for factory testing purposes. TST0–2 should be

tied low for normal operation.

CC1

CC2

Positive power supply input pins. V

=5V ±5%. A 0.1 µF

ceramic bypass capacitor should be connected between

CC1

and GND1, and V

CC2

and GND2.

GND1, GND2

Ground input pins.

Not connected.

Functional Description

Adaptive Differential Pulse Code Modulation (ADPCM) is a

transcoding algorithm for voice and voice band data trans-

mission. The use of ADPCM reduces the channel bandwidth

requirements from the standard 64 kbps PCM signal by a

factor of two or more. It is used for converting a 64 kbps

A-law or µ-law PCM channel to and from a 40, 32, 24 or

16 kbps channel. The 8-bit PCM signal is reduced to 2–5 bits

ADPCM signal depending on the selected bit rate in the en-

coder.

The TP11362A meets the ITU (CCITT) G.726 recommenda-

tion for 40, 32, 24, and 16 kbps ADPCM, as well as ANSI

T1.301 for 32 kbps. Each channel can be operated with an

independently selectable bit rate determined by QSEL1 and

QSEL0 (see

Table 1

TABLE 1. Bit Rate Selection

QSEL1 QSEL0 ADPCM Bit Rate

0 0 32 kbps

0 1 24 kbps

1 0 16 kbps

1 1 40 kbps

The ADPCM encoder converts the 64 kbps A-law or µ-law

PCM input signal to a uniform PCM signal which is sub-

tracted from an estimated signal obtained from an adaptive

predictor. A 31-, 15-, 7-, or 4-level non-uniform quantizer is

used to assign five, four, three or two binary digits, respec-

tively, to the value of the difference signal for transmission.

The ADPCM decoder reconstructs the original PCM signal

by adding the received quantized signal to the signal estima-

tion calculated by the predictor. A synchronous coding ad-

justment unit prevents cumulative distortion occurring on

synchronous tandem codings (ADPCM-PCM-ADPCM) un-

der certain conditions.

The adaptive predictor consists of two independent predictor

structures. One uses a second order recursive filter which

models the poles, and the other uses a sixth order

non-recursive filter which models the zeros in the input sig-

nal. This dual structure enables effective handling of both

speech and voice band data signals.

ADPCM PROCESSING

ADPCM to PCM Decoding Operation

When a logic “0” of TRB is latched in with the falling edge of

CE, the ADPCM processor is set to the decoding mode. Data

applied at the RSI input is sampled with the falling edge of

ASCK into a 5-bit ADPCM serial register. Within the next

cycle of CE, the decoder converts the ADPCM input data to

an 8-bit companded PCM data after 123 master clocks

(CLK). The 8-bit parallel PCM data is loaded into a

parallel-to-serial shift register and shifted out at the RSO out-

put with the rising edges of PSCK.

PCM to ADPCM Encoding Operation

A logic “1” of TRB at the falling edge of CE sets the ADPCM

processor to the encoding mode. Data applied at the TSI in-

put is sampled in an internal 8-bit PCM register with the fall-

ing edge of PSCK. During the next cycle of CE, the encoder

converts the companded 8-bit PCM data into a 5-, 4-, 3- or

2-bit ADPCM data, which will be shifted out during the third

cycle of CE at the TSO output with the rising edges of ASCK.

The TP11362A requires one master clock signal CLK. The

master clock signal CLK is not required to be synchronous to

the serial I/O clocks ASCK or PSCK. The serial interface

uses the serial clocks ASCK and PSCK and chip enable CE

for receiving and transmitting data. The data is internally

synchronized to the master clock CLK. There is a lower limit

of the clock frequency for CLK resulting from the number of

clock cycles required for processing the data.

Table 2

shows

the required clock cycles per channel depending on the se-

lected mode.

TABLE 2. Processing Cycles

Mode of Operation CLK Cycles Needed

Decoder 123

Encoder 123

Initialized Channel 45

Disabled Channel 4

The sampling period (usually 125 µs for 8 kHz frame) divided

by the number of CLK cycles gives the required minimum

CLK period. A slightly higher CLK frequency is used in order

to allow for jitter and inaccuracies in the CLK rate. As an ex-

ample, for a four channel ADPCM codec, CLK frequency is 8

MHz as shown in the following calculations:

CLK

=125 µs /(8 *123) =127.03 ns

CLKmin

=1/t

CLK

=7.872 MHz

CLKnom

=8.0 MHz

The period of CE must be equal to or greater than the re-

quired number of CLK cycles times the period of CLK. CE

must be low for more than 4 CLK cycles.

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Functional Desc ption TCanllnued) The TPITSSQA Ts capable oT precessTng eTghT TndepeerenT channels lhall duplex) oT Tour Tullrduplex PCM channels Wlmln T25 ps Ta kHz) The laglc sTaTe oT THE aT The TallTrTg edge pl CE deTeTanes whroh ThpuT regTsTeT Ts aoTTTre duTTng ThaT CE peTTed and thoh oulpuT regTsTer WT” he aaTTTre Th The lallcwlng ThTrd CE peTTod The Thpul daTa Ts preoessed (FCM daTa ehooded er ADPCM daTa decededl duTThg The second cycle and shTTTed puT Tn The ThTrd oyole pT CE thle CE Ts thh SERIAL l/O lnpuT daTa Ts TrahsleTTed Tnlp The TPITSSQA en The TallTng edge pT The clock sTgnal. thle oquuT daTa Ts TTansmrTTed on The T Thg edge pT The clock sTgnal. PCM daTa Ts Trahslened synchmnausly usTng PSCK‘ thle ADPCM daTa Ts |Tarlsr lerTed synchrannusly usTrTg ASCK The clock sTngals ASCK and PSCK should be thh we CE changes, All seTTal daTa IS TrahslerTed wTTh MsE Tnsl. ﬁgure 2 and ﬁgure ashew The serTal ThpuT and oquuT slluchﬂe: Tespectlvely PCM serlal Inpul Eeglsler The serTal POM daTa Te be encoded Ts shTTTed Tth The Brbll PCM TnpuT TegTsTer Wlm The TallTng edges pT PSCK thle CE and THE are thh. The TallTng edge eT CE laTohes The sTaTe oT TsT escr —Do— cz— TTE Tsl ASEK —Do— The TnpuT regTsTeT ahd Translers The lasT s hlls daTa pm To The GE (Tanslllcn |0 The core Tor pmcessmg The Elm PclT/l Tnpul TegTsTer Ts cleared asyhohmhously wTTh HsTE nghg low. ADPCM serlal Inpul HeglsTer The ADPCM seTTaI TnpuT regTsTer Ts a 57m sthT TegTsTeT To sTore The Srbll daTa m The 40 kbps ADPCM rnode seTTal Thpul daTa Ts laTahed Tn WTTh The TallThg edges ol ASCK thle CE Ts thh and THE Ts law A rnTnTmurn number oT lTue low goTng ASCK pulses rnusT pe avallable WTlhTrT The CE pulse when epeTaTTng Th The AD khps mode For The 32‘ 24 and Te khps modesl ASCK rnusT be pulsed low 4 Trmes thle CE Ts thh To read m The Hsl daTa The TallTng edge pl CE laTahes The lasT 5 bus daTa Tn The 40 kbps mode or The TasT 4 blls daTa Th The 32‘ 2k and Ta kbps rnpdes pm To The CE TTansTsTTprT, see Table 3 Tor The posTTTorT pT The ADPCM daTa Th The ﬁlm Tnpul TegTsTer when 5 ASCK lpw goTrTg pulses poour thle CE Ts thh and THE IS lew ETTT Tn Table as The LSB whlch Ts The lasT ETT Th 32 and AD hops rnedes reTererToed To The negaTTue edge ol CE mu m sml linA TagTsTar .TT "5M ﬁ-ETA mm serlal linA anlshr .T res“ “:D— ”5 RSTB FIGURE 2. serlal lnpuT sldeure ADPCM oulpul EeglsTer The TnTeTnal encoded parallel ADPCM daTa Ts leaded mm The ﬁrm ADFCM oquuT regTsTererh The TallTng edge pl CE Slgr nal. The lTrsT MSB daTa Ts sthTed euT alTeT The rTsTng edge oT CE, supseouenT ADPCM serTal daTa Ts shTTTed puT wTTh The rTsTng edge pl ASCK Table A shows The TransleT order pT The ADPCM equuT daTa IT rine Than 4 ASCK clocks are avallr aple thle CE Ts thh Th The 32, 24‘ and Ta kbps rnpdesl The ADPCM pquuT daTa lel TeorroulaTe sTaTTThg WTlh The ma In The ease oT The 40 kbps model The ADPCM oulpuT paTTeTn TuTll reaTToulaTe, sTarTThg wTTh The MsET wTTh The lTlTh TTsTng edge oT ASCK thle CE Ts thh PCM oulpul Eeglsler The deceded Srblt parallel PclT/l daTa Ts loaded ThTo an 57th parallelrmrserlal equuT shTTT regTsTer wTTh The TallTng edge ol CE The MsE daTa Ts sthTed puT wTTh The leadTng edge pl CE‘ and supseguehT daTa are shTTTed puT Wlm The "Slng edges ol FSCK thle CE Ts thh. The Brbll FCM daTa aT The Hso Our puT WT" TeoTraulaTe erh The MSB lTrsT aTTer The seventh TTsTng edge ol FSCK thle CE Ts thh ﬁgure tshows The lull duplex TTrnTrTg dTagram Tor The AD khps mode FaT The 32 24 and IS khps rnedes only lauTASCK low pulses are needed thle CE Ts thh THE Ts alTerrTaTe thh and low m The lull duplex rnede aT eaoh TallThg edge eT CE Tor a TransrnTT Tehooder) operaTTph Tellewed

Functional Description (Continued)

The TP11362A is capable of processing eight independent

channels (half duplex) or four full-duplex PCM channels

within 125 µs (8 kHz).

The logic state of TRB at the falling edge of CE determines

which input register is active during that CE period and which

output register will be active in the following third CE period.

The input data is processed (PCM data encoded or ADPCM

data decoded) during the second cycle and shifted out in the

third cycle of CE while CE is high.

SERIAL I/O

Input data is transferred into the TP11362A on the falling

edge of the clock signal, while output data is transmitted on

the rising edge of the clock signal. PCM data is transferred

synchronously using PSCK, while ADPCM data is trans-

ferred synchronously using ASCK. The clock signals ASCK

and PSCK should be high while CE changes. All serial data

is transferred with MSB first.

Figure 2

and

Figure 3

show the

serial input and output structures, respectively.

PCM Serial Input Register

The serial PCM data to be encoded is shifted into the 8-bit

PCM input register with the falling edges of PSCK while CE

and TRB are high. The falling edge of CE latches the state of

the input register and transfers the last 8 bits data prior to the

CE transition to the core for processing. The 8-bit PCM input

ADPCM Serial Input Register

The ADPCM serial input register is a 5-bit shift register to

store the 5-bit data in the 40 kbps ADPCM mode. Serial input

data is latched in with the falling edges of ASCK while CE is

high and TRB is low. A minimum number of five low going

ASCK pulses must be available within the CE pulse when

operating in the 40 kbps mode. For the 32, 24 and 16 kbps

modes, ASCK must be pulsed low 4 times while CE is high to

read in the RSI data. The falling edge of CE latches the last

5 bits data in the 40 kbps mode or the last 4 bits data in the

32, 24, and 16 kbps modes prior to the CE transistion. See

Table 3

for the position of the ADPCM data in the 5-bit input

high and TRB is low. Bit 1 in

Table 3

is the LSB which is the

last bit in 32 and 40 kbps modes referenced to the negative

edge of CE.

ADPCM Output Register

The internal encoded parallel ADPCM data is loaded into the

5-bit ADPCM output register with the falling edge of CE sig-

nal. The first MSB data is shifted out after the rising edge of

CE, subsequent ADPCM serial data is shifted out with the

rising edge of ASCK.

Table 4

shows the transfer order of the

ADPCM output data. If more than 4 ASCK clocks are avail-

able while CE is high in the 32, 24, and 16 kbps modes, the

ADPCM output data will recirculate starting with the MSB. In

the case of the 40 kbps mode, the ADPCM output pattern will

recirculate, starting with the MSB, with the fifth rising edge of

ASCK while CE is high.

PCM Output Register

The decoded 8-bit parallel PCM data is loaded into an 8-bit

parallel-to-serial output shift register with the falling edge of

CE. The MSB data is shifted out with the leading edge of CE,

and subsequent data are shifted out with the rising edges of

PSCK while CE is high. The 8-bit PCM data at the RSO out-

put will recirculate with the MSB first after the seventh rising

edge of PSCK while CE is high.

Figure 4

shows the full duplex timing diagram for the 40 kbps

mode. For the 32, 24 and 16 kbps modes only four ASCK low

pulses are needed while CE is high.

TRB is alternate high and low in the full duplex mode at each

falling edge of CE for a transmit (encoder) operation followed

DS012877-4

FIGURE 2. Serial Input Structure

www.national.com 4

Functional Desc ption {Conﬁrmed} by a reoewe (decoder) opereudh For \he encodlng cpevar “an the PCM dare rs srdred In me 87b“ shrn regrsrer er me Valllng edge ov CE whrle THE rs mgh The TPHSSEA pmr oesses me da|a whnrn 123 CLK pendds dunhg me ﬁallowlng oyoTe ov CE, The encoded ADFCM data rs Tdaded In|a me am pava‘leHusena‘ ampm regrsrer whh rne Valhng edge 0! CE. The MSE data rs shrued our Irrsr whh \he leadmg edge 0! CE‘ and subsequent data rs shrhed dm whh rne nsmg edge M ASCK Fdr me decudlng cperatlcn‘ rne ADPCM da|a rs Tarched and rrensverred to me core at me Va‘llng edge m CE wm‘e TRE rs m The dare rs processed wnhm 123 CLK per node and me decoded 57m FCM dare rs shmed cor wrrn me MSE hrsr. FSCK and ASCK are me docks Tor me PCM and ADPCM da|a sueams‘ respeorwely They musr be hrgn dunhg me rrensmdh M CE. No|e rnar FSCK and ASCK are shown as ga|ed docks as an uphon m conserve power PSCK and ASCK need onTy be valid whrTe CE rs hrgn. 5 —/— D r 575d um “E m" PareHeHdrSena‘ ow ere, T30 m— laws me n u u n lsow vws —Dﬂ escr— m damn st —0 mad yordHaT-ln-Serm Mr. new." 8 _/_ D FIGURE 1. Serial Output Structure

Functional Description (Continued)

by a receive (decoder) operation. For the encoding opera-

tion, the PCM data is stored in the 8-bit shift register at the

falling edge of CE while TRB is high. The TP11362A pro-

cesses the data within 123 CLK periods during the following

cycle of CE. The encoded ADPCM data is loaded into the

5-bit parallel-to-serial output register with the falling edge of

CE. The MSB data is shifted out first with the leading edge of

CE, and subsequent data is shifted out with the rising edge

of ASCK. For the decoding operation, the ADPCM data is

latched and transferred to the core at the falling edge of CE

while TRB is low. The data is processed within 123 CLK pe-

riods and the decoded 8-bit PCM data is shifted out with the

MSB first.

PSCK and ASCK are the clocks for the PCM and ADPCM

data streams, respectively. They must be high during the

transition of CE. Note that PSCK and ASCK are shown as

gated clocks as an option to conserve power. PSCK and

ASCK need only be valid while CE is high.

DS012877-5

FIGURE 3. Serial Output Structure

5 www.national.com

Functional Description {Continued} Anna... Sons 3.: c3 5235 9:5: 355 __._u_ .q mzaui : ; ; 5:8 2: E E; G,Nr;@» o3 2; E55 3 E,” .2 xum< 9;="" s="" “e="" o5="" :5="" :95="" .3="" z="" 5="" xumn="" _kk="">

Functional Description (Continued)

DS012877-6

FIGURE 4. Full Duplex Timing Diagram (40 kbps ADPCM mode)

www.national.com 6

Functional Desc ption {Conunued} mm m 5m am Derndeﬂ aw) mmm m 5mm w mm m mm) cmm N mm m m) FIGURE 5. Full Duplex Tmung Diagram (32 khps ADPcM mode) 2mm N 0mm N a.“ m vow) w m 7, x o x a o i ,~ —, U E k a a a = 3 m i 3 n < 5="" a="" g="" z="" o="" tablejshuwsme="" pusmnn="" auneadpcm="" dammme="" 5mm="" (ransierred="" m="" the="" core="" var="" prunessmg="" m="" we="" 32,="" 24="" and="" pu|="" regmer="" when="" me="" asck="" law="" gamg="" pmses="" ave="" avaname="" 16="" kbps="" modes,="" in="" me="" 40="" kbps="" made,="" me="" \as\="" we="" nus="" punr="" wnne="" ce="" ‘5="" mgn.="" omy="" me="" ‘35!="" mm="" bus="" a!="" me="" adpcm="" mpm="" regwster="" pnur="" m="" we="" valhng="" edge="" a!="" ge="" ave="" lamhed="" m="" and="">

Functional Description (Continued)

Table 3

shows the position of the ADPCM data in the 5-bit in-

put register when five ASCK low going pulses are available

while CE is high. Only the last four bits of the ADPCM input

transferred to the core for processing in the 32, 24 and

16 kbps modes. In the 40 kbps mode, the last five bits prior

DS012877-7

FIGURE 5. Full Duplex Timing Diagram (32 kbps ADPCM mode)

7 www.national.com

Functional Desc ption (Continued) 1a The vaiirng edge ov CE are iaianed rn in Table 3, me iasi in par ari pnor ia To me CE vaiirng edge rs ine LSE ov me ADV RcM daia ward Noie war we serrai rnpai daia rs reverenaed 1a The vaiimg edge av CE winie me senai ouipai daia is reierenaed ia \he nsmg edge av CE T5i and HSI rnpui daia are aioaked in wrin \he vaise edge ov PSCK and A5cr<. respeonveiy="" the="" mse="" av="" t50="" and="" r50="" auipui="" daia="" are="" snrvied="" aui="" wrin="" me="" vaiirng="" edge="" ov="" ce="" 5aaseaaeni="" t50="" and="" h50="" daia="" are="" snrned="" aui="" wrin="" ine="" nsrng="" edges="" ov="" asck="" and="" psck="" respeairyeiy="" taole="" a="" snows="" me="" iransier="" order="" av="" me="" adpcm="" auipai="" daia="" in="" me="" case="" wnere="" there="" are="" more="" asck="" clocks="" man="" the="" adpcm="" daia,="" \he="" adpcm="" ouipui="" wrii="" rearrauiaie="" fm="" exampie,="" v="" we="" 32="" khps="" mode="" rs="" seieaied,="" and="" ergni="" iaw="" puises="" av="" asck="" exis|wiihin="" ine="" ce="" nrgn="" puise,="" ine="" vaiiawrng="" adpcm="" encoded="" daia="" 03702701700703702701700="" wrii="" ap="" pear="" at="" \he="" t50="" ouipui="" (table="" 5)="" table="" 5.="" transier="" order="" oi="" adpcm="" inpul="" daia="" (rsi).="" tne="" lasi="" ell="" prior="" «0="" me="" failing="" edge="" oi="" ce="" is="" the="" lee="" (:1="" (he="" adpcm="" dara="" osel1="" oseln="" ilidde="" el!="" 5="" an="" 4="" el!="" 5="" bll="" 2="" 5|!="" 1="" n="" o="" 32="" kbps="" x="" d3="" d2="" 01="" do="" 0="" 1="" 2d="" kbps="" x="" d2="" d1="" d0="" x="" 1="" 0="" 15="" kbps="" x="" 01="" do="" x="" x="" 1="" v="" «n="" kbps="" d4="" d3="" d2="" 01="" do="" (mse)="" (lse)="" nov.="" 1:="Dani" cam="" sum="" table="" 4.="" transier="" order="" oi="" adpcm="" output="" dara="" (tso)="" mm="" 4="" asck="" rising="" edges="" whiie="" ce="" is="" hign="" (ihe="" firsi="" bi!="" is="" me="" mse="" daia="" an="" (oiiowing="" the="" rising="" edge="" oi="" ce)="" osel1="" oseln="" ilidde="" el!="" 5="" an="" 4="" el!="" 5="" bll="" 2="" 5|!="" 1="" n="" o="" 32="" kbps="" 03="" d2="" d1="" d0="" 03="" n="" 1="" 2d="" kbps="" d2="" 01="" do="" x="" d2="" 1="" 0="" 15="" kbps="" d1="" d0="" x="" x="" d1="" 1="" v="" «n="" kbps="" d4="" d3="" d2="" 01="" do="" (mse)="" (lse)="" nov.="" 2:="unknown" (but="" delirium="" siam="" table="" 5.="" transier="" order="" oi="" adpcm="" oulpul="" daia="" (tso)="" wllh="" 7="" asck="" rising="" edges="" (a="" law="" pulses)="" oi="" asck="" wniie="" ce="" is="" high="" osel1="" oseln="" mode="" an="" a="" ell="" 7="" 5|!="" 6="" an="" 5="" el!="" a="" an="" :i="" ell="" 2="" 5|!="" 1="" a="" 32="" kbps="" d3="" d2="" d1="" d0="" 03="" d2="" 01="" on="" n="" 1="" 2a="" kbps="" d2="" 01="" on="" x="" 02="" d1="" d0="" x="" 1="" 0="" 15="" kbps="" d1="" d0="" x="" x="" 01="" dd="" x="" x="" 1="" v="" 40="" kbps="" no="" 03="" d2="" 01="" do="" no="" 03="" d2="" now.="" a:="unknown" (but="" delirium="" siam="" single-channel="" imitialization="" and="" all-channel="" reset="" tne="" tr11352a="" adfcm="" proaessar="" can="" he="" rnrirairzed="" on="" a="" perrchannei="" oasrs="" via="" the="" use="" av="" nt="" or="" an="" an="" aiirchannel="" bar="" srs="" via="" me="" use="" ov="" hste="" in="" bum="" cases,="" we="" rniernai="" adpcm="" variabies="" are="" rnrirairzed="" ia="" ine="" devaaii="" vaiues="" as="" suggesied="" by="" \he="" itu="" g="" 725="" reoommendanon="" an="" rndryrduai="" anannei="" can="" he="" mrirairzed="" to="" me="" desrred="" cunr="" vrgarairan="" oy="" seiimg="" ine="" aarrespondrng="" daia="" variabies="" pciliv,="" en,="" 05mm)="" and="" by="" assenrng="" \he="" init="" pin="" nrgn="" tne="" cunr="" vrgarairan="" daia="" and="" nt="" srgnai="" are="" siraaed="" ai="" ine="" vaiirng="" edge="" 0!="" ce="" for="" an="" rnrirairzairan="" cycle,="" the="" penod="" ov="" ce="" musi="" oe="" a5="" masier="" ciock="" (clk)="" ayaies="" tne="" iransaader="" rs="" inen="" ready="" ia="" process="" we="" nexi="" anannei="" tne="" aonve="" low="" rstb="" srgnai="" is="" used="" vor="" a="" warm"="" resei="" as="" well="" as="" var="" vaaririairng="" devroe="" iesnng="" tner="" irairzairan="" ai="" iire="" rniernai="" memory="" iakes="" 72s="" clk="" ayaies="" avier="" iire="" rste="" gaes="" inac|ive="" (iagro="" *1")="" tne="" vrrsi="" iransriron="" ov="" ce="" is="" aiiowed="" six="" clk="" ayaies="" aiier="" rstb="" gaes="" rnaonve="" ii="" is="" reaammended="" inai="" ce="" oe="" kepi="" low="" danng="" ine="" rnrirairzairan="" pnase="" the="" vecr="" ommended="" vaiues="" vor="" asck="" and="" psck="" dunng="" rnrirairzairan="" are="" iagro="" -1="" and="" ma="" vor="" t5i="" and="" rsi="" iogra="" “a"="" any="" daia="" (ts="" and="" r5i)="" applied="" during="" ine="" rnrirairzairan="" pnase="" will="" be="" iasi,="" however.="" they="" won="" |="" aiveai="" the="" proper="" rnrnairzairon="" process="" tne="" mrnrmum="" iow="" irme="" av="" hstb="" rs="" 2="" clk="" ayaies="" tne="" chip="" vesumes="" aperanon="" an="" we="" vrrsi="" neganve="" edge="" av="" ce="" avier="" ine="" aampieiran="" 0!="" me="" rnrnairzairan="" power-on-reset="" tne="" anranrp="" paweponrhesei="" macro="" rs="" aonvaied="" wnen="" exterr="" nai="" power="" is="" irrsi="" appired="" iaine="" devroe="" ii="" nas="" “is="" same="" vuncr="" iron="" as="" me="" exiernai="" rstb="" pin="" wnron="" mrirairzes="" aii="" onanneis="" 1a="" the="" devauii="" yaiues="" deirned="" in="" me="" itu="" heaammendairan="">

Functional Description (Continued)

to the falling edge of CE are latched in. In

Table 3

, the last in-

put bit prior to to the CE falling edge is the LSB of the AD-

PCM data word.

Note that the serial input data is referenced to the falling

edge of CE while the serial output data is referenced to the

rising edge of CE. TSI and RSI input data are clocked in with

the false edge of PSCK and ASCK, respectively. The MSB of

TSO and RSO output data are shifted out with the falling

edge of CE. Subsequent TSO and RSO data are shifted out

with the rising edges of ASCK and PSCK respectively.

Table 4

shows the transfer order of the ADPCM output data.

In the case where there are more ASCK clocks than the

ADPCM data, the ADPCM output will recirculate.

For example, if the 32 kbps mode is selected, and eight low

pulses of ASCK exist within the CE high pulse, the following

ADPCM encoded data D3-D2-D1-D0-D3-D2-D1-D0 will ap-

pear at the TSO output (

Table 5

TABLE 3. Transfer Order of ADPCM Input Data (RSI). The Last Bit Prior

to the Falling Edge of CE is the LSB of the ADPCM Data

QSEL1 QSEL0 Mode Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps x D3 D2 D1 D0

0 1 24 kbps x D2 D1 D0 x

1 0 16 kbps x D1 D0 x x

1 1 40 kbps D4 D3 D2 D1 D0

(MSB) (LSB)

Note 1: x=Don’t Care state

TABLE 4. Transfer Order of ADPCM Output Data (TSO) with 4 ASCK Rising Edges

while CE is High (the First Bit is the MSB Data Bit following the Rising Edge of CE)

QSEL1 QSEL0 Mode Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps D3 D2 D1 D0 D3

0 1 24 kbps D2 D1 D0 x D2

1 0 16 kbps D1 D0 x x D1

1 1 40 kbps D4 D3 D2 D1 D0

(MSB) (LSB)

Note 2: x=unknown (but defined) state

TABLE 5. Transfer Order of ADPCM Output Data (TSO)

with 7 ASCK Rising Edges (8 Low Pulses) of ASCK while CE is High

QSEL1 QSEL0 Mode Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 0 32 kbps D3 D2 D1 D0 D3 D2 D1 D0

0 1 24 kbps D2 D1 D0 x D2 D1 D0 x

1 0 16 kbps D1 D0 x x D1 D0 x x

1 1 40 kbps D4 D3 D2 D1 D0 D4 D3 D2

Note 3: x=unknown (but defined) state

SINGLE-CHANNEL INITIALIZATION AND

ALL-CHANNEL RESET

The TP11362A ADPCM processor can be initialized on a

per-channel basis via the use of INIT or on an all-channel ba-

sis via the use of RSTB. In both cases, the internal ADPCM

variables are initialized to the default values as suggested by

the ITU G.726 recommendation.

An individual channel can be initialized to the desired con-

figuration by setting the corresponding data variables PCM1,

EN, QSEL(0,1) and by asserting the INIT pin high. The con-

figuration data and INIT signal are strobed at the falling edge

of CE. For an initialization cycle, the period of CE must be 45

master clock (CLK) cycles. The transcoder is then ready to

process the next channel.

The active low RSTB signal is used for a “warm” reset as

well as for facilitating device testing. The initialization of the

internal memory takes 726 CLK cycles after the RSTB goes

inactive (logic “1”). The first transition of CE is allowed six

CLK cycles after RSTB goes inactive. It is recommended

that CE be kept low during the initialization phase.The rec-

ommended values for ASCK and PSCK during initialization

are logic “1”, and that for TSI and RSI logic “0”. Any data (TSI

and RSI) applied during the initialization phase will be lost,

however, they won’t affect the proper initialization process-

.The minimum low time of RSTB is 2 CLK cycles.

The chip resumes operation on the first negative edge of CE

after the completion of the initialization.

POWER-ON-RESET

The on-chip Power-On-Reset macro is activated when exter-

nal power is first applied to the device. It has the same func-

tion as the external RSTB pin which initializes all channels to

the default values defined in the ITU Recommendation

www.national.com 8

Functional Desc ption loonlrndedl G726. A| power up, we outpuls T50 and H50 are m TRLSTATE mode. Tnls "cold” resel process IS asynchronous and lakes applaxlmalely 2000 CLK cycles lor lne lmllallzar non. Dunng me resel process, we oulpuls T50 and R50 are H1 THLSTATE rnode, CHANNEL NOP ann onannel can be lndependemly dlsabled. wnen EN ‘5 3| logle low on me Valllng edge ol CE‘ lne ADPCM lransooder pracessmg lor lnal channel ‘5 dlsabled. Tne processor ler qulres A CLK oyoles lor CE lo malmaln all onennel venahles. Tne dale outpul porls are also placed m known slales. Aller llus me processor walls lor me next lnterrupl Pcwer l5 con served durlng lms (lme by dlsabhng me .nlernel reglslers. TSO oulpols \he lollowmg da|a aﬂer a channel NOP TABLE 6.150 al channel NOP osELl DSELD Made TSO o o 32 kbps 0 o a o 1 2d kbps 0 o a o o ls kbps 0 o a o 1 40 kbps 0 o a o n Tne dale panem al T50 m Table aare shown wllh 3 ASCK rlsmg edges wunln lne CE hlgl’l pulse lor \he 32‘ 2d. ls kbps modes and A ASCK nslng edges wlmln lne CE hlgl’l pulse lor me 40 kbps mode lme M55 ‘5 smlled oul wlll'l lne lellmg edge ol CE), ln lne ldle case (NOP) wnere EN ‘5 low a| llre lalllng edge ol CE, lne TSO oulpul ‘5 low lor me durallcm ol me hlgl’l CE pulse ln lne .dle slale (NOF), H50 oulpuls lne lollowmg da|a (hl| represenlauon wl|h me Slgmbl‘ on me lell lollowed by me MSE, \he slgnrbﬂ ‘5 me llrsl on aller lne [lsmg edge ol CE) YAELE 7. R50 at channel NOP PCM1 Mode H50 0 BrBllurLaw 11111111 1 ErEllArLaw llololol

Functional Description (Continued)

G.726. At power up, the outputs TSO and RSO are in

TRI-STATE mode. This “cold” reset process is asynchronous

and takes approximately 2000 CLK cycles for the initializa-

tion. During the reset process, the outputs TSO and RSO are

in TRI-STATE mode.

CHANNEL NOP

Each channel can be independently disabled. When EN is at

logic low on the falling edge of CE, the ADPCM transcoder

processing for that channel is disabled. The processor re-

quires 4 CLK cycles for CE to maintain all channel variables.

The data output ports are also placed in known states. After

this the processor waits for the next interrupt. Power is con-

served during this time by disabling the internal registers.

TSO outputs the following data after a channel NOP:

TABLE 6. TSO at Channel NOP

QSEL1 QSEL0 Mode TSO

0 0 32 kbps 0000

0 1 24 kbps 0000

1 0 16 kbps 0000

1 1 40 kbps 00000

The data pattern at TSO in

Table 6

are shown with 3 ASCK

rising edges within the CE high pulse for the 32, 24, 16 kbps

modes and 4 ASCK rising edges within the CE high pulse for

the 40 kbps mode (the MSB is shifted out with the falling

edge of CE). In the idle case (NOP) where EN is low at the

falling edge of CE, the TSO output is low for the duration of

the high CE pulse.

In the idle state (NOP), RSO outputs the following data (bit

representation with the sign-bit on the left followed by the

MSB, the sign-bit is the first bit after the rising edge of CE):

TABLE 7. RSO at Channel NOP

PCM1 Mode RSO

0 8-Bit µ-Law 11111111

1 8-Bit A-Law 11010101

9 www.national.com

Absolute Maximum Ra gs (Nole 'NO TGT. FNXrei NSOASS') II MIIIIary/Aeraspace specIIIed devIces are required. pleas! counsel lhe Nalinnal Semiconduclm Sales Oﬂica/ Distributors lor avallabllily and specifications. vcc Io GND 7v VoIIage aI Any DIgIIaI Inpms or Outpuis GND 7 0 3V Io vcc + 0 av DC Electrical Characteristics srorage Temperame Range Lead Temperaiure (soldenng, 10 sec) LaIcnup Immunny on any PIn 04A {281m PLCC) 04A {247nm DIP) rAEVC Io A250 3000 :75 mA 7aVc/w AaVc/w unIess mherwIse nored, IImIIs pnnIed in bold charadevs are guarameed Iorvcc s 5 0v 1 5%, GNDI = GND2 s W, TA e 7400 Id .050 by ooneIauon mm 100% eIeoInoaI (esilng aI TA s 250 AII omer IImI|s are assured by oorreIauon mm are pruducmn Iesrs and/er produci desrgn and characienzaucn TypIcai vaIues are spedIIed aI VCC = s5v, TA . 25'c Symbol Paramerer condIIIons Min Typ Max unIrs ICC” SuppIy Currem CLK = 0 0 MHz HSTB = Low 1.0 mA IPower Down Mode) ICC, SuppIy Currem CLK = 0 0 MHz HSTB = HIgh 7 9 mA IPower Up Mode) FD Fewer DISSIpaIIon 35 mW er Inom Low VoIIage ASCK, FSCK CE, THE, 0.0 v v,H Inom HIgh VoIIage CLK, RSTE 2.0 V W Inom Low VoIIage PcMI HSI TSI, OSELO, n.7 v v,H Inom HIgh VoIIage osELI, INIT, EN 2.0 v v0L 00mm Law Manage IL = 4 mA 0.4 v vON 00mm HIgh VoIIage I ,4 mA 2.0 v IL . 70 4 mA, vcc . A 75v vac _ 0.3 v I,L Inom Low CurrenI GND < v,n="">< v,l="" ah="" signai="" |npu|s="" —m="" m="" im="" inom="" high="" curreni="" vm="">< v,n="">< vcc="" ali="" signai="" inputs="" 10="" 0a="" tes|="" inputs="" tstd="" tsti,="" tst2="" (noie="" a)="" 150="" 0a="" ioz="" 00mm="" correnr="" in="" high="" gnd="">< v0="">< vcc,="" t50="" and="" r50="" —id="" 10="" m="" impedance="" siaie="" c,="" inom="" capacnance="" i0="" pf="" 00="" 00mm="" capacnance="" i0="" pf="" cl="" capacmve="" load="" i00="" pf="" no!-="" a:="" test="" mums="" nm="" inmmai="" duh="" dawn="" msismv="" timing="" speciﬁcations="" uniess="" otherwise="" noied,="" iimiis="" pnnred="" in="" bold="" characiers="" are="" guaranreed="" ior="" vcc="5" 0v="" i="" 5%,="" gndi="" s="" gnd2="" .="" 0v="" ta="" _="" 740‘s="" re="" +050="" by="" carrelahon="" wnn="" 100%="" eiecincai="" |esmg="" ai="" ta="" 25‘s="" aii="" oiner="" rmns="" are="" assured="" by="" coneiamn="" wlih="" omer="" omduouon="" iesis="" andor="" product="" design="" and="" charactenzamn="" typlcal="" vaiues="" are="" specmed="" ai="" vcc=".av," ta="" a="" 250="" symbol="" parameter="" commons="" mln="" yyp="" max="" uniis="" iclk="" clk="" frequency="" (noie="" 5)="" assummg="" 50%="" duty="" cycle="" 7="" a="" 0.0="" is="" mhz="" iclk="" clk="" duterycle="" a0%="" 50%="" 50%="" clk="" pendd="" ir="" rise="" trme="" iclk,="" ce,="" i0="" ns="" asck,="" fsck)="" if="" faii="" time="" (clk,="" ce="" i0="" ns="" asck,="" fsck)="" icep="" ce="" penod="" encode="" or="" decode="" i23="" clk="" iniiiaiizaiion="" a5="" cones="" disabie="" 9="" im="" ce="" pulse="" worn,="" low="" 4="" clk="" cones="">

Absolute Maximum Ratings (Note *NO

TGT: FNXref NS0465*)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

to GND 7V

Voltage at Any Digital

Inputs or Outputs GND − 0.3V to V

+ 0.3V

Storage Temperature Range −45˚C to +125˚C

Lead Temperature

(Soldering, 10 sec) 300˚C

Latch-up Immunity on any Pin ±75 mA

(28-pin PLCC) 79˚C/W

(24-pin DIP) 49˚C/W

DC Electrical Characteristics

Unless otherwise noted, limits printed in bold characters are guaranteed forV

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

CC0

Supply Current CLK =8.0 MHz, RSTB =Low 1.8 mA

(Power Down Mode)

CC1

Supply Current CLK =8.0 MHz, RSTB =High 7 9mA

(Power Up Mode)

Power Dissipation 35 mW

Input Low Voltage ASCK, PSCK, CE, TRB, 0.8 V

Input High Voltage CLK, RSTB 2.4 V

Input Low Voltage PCM1, RSI, TSI, QSEL0, 0.7 V

Input High Voltage QSEL1, INIT, EN 2.0 V

Output Low Voltage I

=4mA 0.4 V

Output High Voltage I

=−4 mA 2.4 V

=−0.4 mA; V

=4.75V V

− 0.8 V

Input Low Current GND <V

, All Signal Inputs −10 µA

Input High Current V

, All Signal Inputs 10 µA

Test Inputs TST0, TST1, TST2 (Note 4) 150 µA

Output Current in High GND <V

, TSO and RS0 −10 10 µA

Impedance State

Input Capacitance 10 pF

Output Capacitance 10 pF

Capacitive Load 100 pF

Note 4: Test inputs have internal pull-down resistor.

Timing Specifications

Unless otherwise noted, limits printed in bold characters are guaranteed for V

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

CLK

CLK Frequency (Note 5) Assuming 50%Duty Cycle 7.9 8.0 16 MHz

CLK

CLK Duty-Cycle 40%50%60%CLK

Period

Rise Time (CLK, CE, 10 ns

ASCK, PSCK)

Fall Time (CLK, CE, 10 ns

ASCK, PSCK)

CEP

CE Period Encode or Decode 123 CLK

Initialization 45 Cycles

Disable 9

CEL

CE Pulse Width, Low 4CLK

Cycles

www.national.com 10

Timing Speciﬁcations {Conunued} Umess omemse no|ed hmus prmted m bold charamers are guaranteed Ter VCC = 5 av 1 5%, GND1 a GND2 nv, TA 740's (0 +550 by curre\a\|on mm 100% eTecmeaI lestmg at TA a 250 AH other hmns are assured by eenelamn mm emer proeeeuen (esTs ammm pmduct dawn and charadeuzahon TypTeaI vames are speemed at VCC = +5v, TA a 290 Symbol Parameler Condlllons Mln Typ Max Unlls (Hum How We CE low aher me CE Low 15 ns PSCK’ASCK Men (MEN Semp TTme, CE Men Eeiore me CE Low 15 ns PSCK’ASCK Law (we TRB Hem Tme me CE Low 2n ns (was THE Setup TTme me ASCK Low ane FSCK Low 2n ns (,5 T5, RSI semp TTme me ASCK Low ane FSCK Low 2n ns (M T5T, RSI Hold Time me ASCK Low ane FSCK Low 2n ns 1mm“ PSCK’ASCK Men and 55 ns Low TTmes (0N T50, RSO Tum On Tme me CE Hen 4n ns (OD T50, RSO onpagamn me ASCK Hugh er PSCK HTgn 4n ns DeTay We 10,; T50, RSO Tum on Tme me CE Low 2n ns wane Dam (a TRIVSTATE) (:5 Semp me Im comm me CE Low sTgnaTs (MT, EN 2n ns PCM1,0SEL1 QSELO) to, How We my Conuo‘ me CE Low sTgnaTs (MT, EN 2n ns PCM1,0SEL1 QSELO) (Rm HSTB Pulse wTem Lew 2 CLK Cyc‘es (we HSTB High To me Fursl a CLK CE HighrLow Transmcn Cyc‘es mu. 5: me; my 3 mu duwux Idncndmg m meemm m a raw deem Idncadmg or cnmdmm mm; upcraunn m a ‘25 us emu

Timing Specifications (Continued)

Unless otherwise noted, limits printed in bold characters are guaranteed for V

=5.0V ±5%, GND1 =GND2 =0V, T

−40˚C to +85˚C by correlation with 100%electrical testing at T

=25˚C. All other limits are assured by correlation with other

production tests and/or product design and characterization. Typical values are specified at V

=+5V, T

=25˚C.

Symbol Parameter Conditions Min Typ Max Units

HDCEL

Hold Time, CE low after From CE Low 15 ns

PSCK/ASCK High

SUCEH

Setup Time, CE High Before From CE Low 15 ns

PSCK/ASCK Low

TRBH

TRB Hold Time From CE Low 20 ns

TRBS

TRB Setup Time From ASCK Low and PSCK Low 20 ns

TSI, RSI Setup Time From ASCK Low and PSCK Low 20 ns

TSI, RSI Hold Time From ASCK Low and PSCK Low 20 ns

PSCK/ASCK

PSCK/ASCK High and 55 ns

Low Times

TSO, RSO Turn On Time From CE High 40 ns

TSO, RSO Propagation From ASCK High or PSCK High 40 ns

Delay Time

OFF

TSO, RSO Turn Off Time From CE Low 20 ns

(Valid Data to TRI-STATE)

Setup Time for Control From CE Low

Signals (INIT, EN, 20 ns

PCM1, QSEL1, QSEL0)

Hold Time for Control From CE Low

Signals (INIT, EN, 20 ns

PCM1, QSEL1, QSEL0)

RSTL

RSTB Pulse Width Low 2 CLK

Cycles

RSTH

RSTB High to the First 6 CLK

CE High-Low Transition Cycles

Note 5: Values for 4 full-duplex (decoding and encoding) or 8 half-duplex (decoding or encoding) channels operation in a 125 µs period.

11 www.national.com

Timing Specifications (Cummued) Es: Sunni .u manor. 1? r; o r a. ,1} iii; 3} r\ E, i i 1/ \ E / \ / \ » 2,: :2 E: :2 ICICIC E. E. oidmo .23 5:76 B: omk Em xum< 0mm="" ,5="" 5e="">

Timing Specifications (Continued)

DS012877-8

FIGURE 6. ADPCM Timing

www.national.com 12

Applications Information Emnlﬂv: emu .x c I W, m 5 D D \l Ur‘MerIace W: I p I >0): C E C D D I mm IIIIII sub-mm" I I I I I m DR mm _..o : SUE I I 11:3an TPIISsQAm m “3057 ver ‘—Imm I : UID ADPCM COMBO' : I é —> rsn I I 3 —> rsx I 5 O 3 O a —> saw I I E 's E E 4 a 5 I I l I I I I DR I I TP3057 H m/Irnm SUC I I W I Mux/Demux I m mm"; mm DR I TP3057 <—> III/m 5U: : I ASIC m I I I I an I ' TP3057 Him/Hum m I m . I I FIGURE 7. 'IypIcal AppIIcaIIon In an ISDN PaIr Galn System

Applications Information

DS012877-9

FIGURE 7. Typical Application in an ISDN Pair Gain System

13 www.national.com

Applications Information (Cummued) r ‘ ‘ ‘ ‘ ‘ )SCK/BCLKX / x ‘ ‘ ‘ l , WSW W @namaanmo , BCLKX/ASCK W ‘n ‘5‘ «Mancunian» Now. a: m aw cm at as can he :dmsmd m mam m dmnmm PcM am m mm m we comm Nov. 7: m Dx m amnm ‘5 5mm" wwh me my van"; Sync mm m mm dau mung mom-‘1 FIGURE 3. Example 0! a nmlng Inlerlace helween an mum and a COMBO

Applications Information (Continued)

DS012877-10

Note 6: The duty cycle of CE can be adjusted to adapt to different PCM data bit clocks of the COMBO.

Note 7: The DX data output is shown with the long frame sync mode (non-delayed data timing mode).

FIGURE 8. Example of a Timing Interface between an ADPCM and a COMBO

www.national.com 14

Physical Dimensions mas (minimums) unless omerwlse noted I 10er m 4115742 2m mammwmmmmmmmi, ‘ 1 nm ‘ l “-315; i "mm; 1 mm 1:1 mi m. ”nm\ ‘ . i . . mmmmmmmmmwmw ualrsnaunmis mmmmm ansnlonvwwrlcunnmn mm mm m , Iwwruml m m ‘T unusual i uszu g A #, 1i " ‘5 #322132, was , "mm-us ‘ nnwnmi ’ 41 5.151335 ' warm _ mu... ‘ Rsuznzw 24»Lead (0.600" Wide) Molded Dual-In-une Package Order Number TPIIJBZAN NS Package Number N2IA

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead (0.600" Wide) Molded Dual-In-Line Package

Order Number TP11362AN

NS Package Number N24A

15 www.national.com

TP11362A Quad Adaptive Different al PCM Processor Physical Dimensions Inches IiiiiiiiiiietersI uniess otherwise nuied (Cummued) .n m ennno .n IE [it uan ntsa PIN vi mm ‘5‘ " [i H] I 25 n 0292i) mm, [0 ma ID] In moasi 1 25 L: i is ”i 1:“qu i‘l [I17] am TVP—. iTezi nuts tsn x , Ii H] i? Isa-a wow [I ie-t 57] 0 mm 005 Iiz mo izI "P ZE-Lead Molded Plastic Leaded chip Carrier Order Number TPiuezAv NS Package Number vzaA LIFE SUPPORT POLICY tints i‘lnlnanmwp DAIMHDZD w [intimsi] P [SEATING mu: um - ‘ Iiiri it» In iii a instauisw Luna 3!} a cum [0 NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein 1. Lite support devices oi systems are devices or sys- 2. A critical component in any cphipohentoi z Iiie support terns which, (a) are intended tor sulgicai Impiznl into device or system whose iaiiure to penorhi can be vea- the body‘ oi (m support 0! sustain Me and whose iaii- sonzbly expected to cause the iaiiure at the iiie support ure to periorm when properiy used in accordance device or system prtp aiiect its sziety or eiiectiveriess, with instructions tor use pvovIded in the labeiing‘ can be veasonabiy expecled to resuit in a signiiicaht mum is the user, Naimnai somicuntluclar Nalinnal smcmm. Mali-mm summon" cam-2mm" some. mic KEN; uﬂ. smeiisss m «QIOIIEDSZIDESEE inhrissi sirsiehieiest Yei iaaczrziese Emsii ewe-sweaiiehssm omiicehiie scshishhs Fix IEnn7JT7DI! mum Yei «eiuiicomsscs rmhsisui Kwiseh mi suppohtehssssm wish Yei .teiniaosazmz HOWKDR! rishssis Yei «QIOIIEDSIIZMSE Tei isszi 27171600 wwwnaiinnaiwm iisiim Yei .tein i anﬁaoisau m iaﬁziznsagsn Hﬂinnal Smicnnﬂuﬂul Japan tut. r.i ti 3 552a 5175 Fax 311 am 517‘!

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-

VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

www.national.com

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Japan Ltd.

Tel: 81-3-5620-6175

Fax: 81-3-5620-6179

28-Lead Molded Plastic Leaded Chip Carrier

Order Number TP11362AV

NS Package Number V28A

TP11362A Quad Adaptive Differential PCM Processor

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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